[SOLVED] SAR adc comparator speed

[pankajpc]

I just interviewed with a company and they asked me the Comparator clock rate for SAR adc. I said
(number of bits X clock rate).

So for a 10bit/ 5msps SAR adc, it will be given by 50us (conversion time) So what is the clock rate for comparator

Is it reciprocal

Hoping a prompt response.


regards
-pc

 

[dick_freebird]

The comparator will be clocked once per bit. Its delay plus
the DAC settling time (to 1/2 LSB) and SAR logic delay all
have to fit into the bit-time window.

In your 5MSPS 10 bit ADC that means 50MHz clock rate.
You have to do 10 compares w/ logic action, to get the
output word and the word comes once per sample (hold).

Your conversion time at 5MSPS is 200nS, not 50uS. Or
conversely, a 50uS conversion time indicates a 20kS/s
word rate. Assuming no overhead for things like a data
latch to output cycle added on, etc.

 

[pankajpc]

If I understood you right, for 10 bit / 5msps, the conversion time per bit will be 200ns. Also, the S/H will sample every 50MSPS. So, it will take 10 (N, number of bits) clock cycles before S/H samples a new Vin. In that time, comparator along with logic and dac settling will go through the binary algorithm 10 times (10, number of bits) in 50msps

Please clear the confusion.


If it is 12 bit sar adc at 5 msps then the clock rate will be 60MHZ or the conversion time will still be 200ns.
reciprocal of conversion time is comparator speed. Also, does it mean that S/H has to settle to 10 bits in 60MHZ.

Please do reply thanks.
regards

 

[dick_freebird]

No, a SAR ADC samples once per word (and has to hold with
sub-LSB droop, for the duration). But it performs N compares,
as it dials in the binary search. You would need the S/H to
settle within, I expect, maybe half a cycle. Positioning the
sample-to-hold transition relative to conversion-start is
probably something of a judgment call, you need to have it
nicely settled but not give it any more time to droop than
necessary.

 

[pankajpc]

Does it mean that N compares are done in N clock cycles. If that is the case then s/h will have a clock of 50 MHZ (Number of bits X Sample rate) and N compares will be done at every 5MHz each. Does that mean that conversion time is 200ns for comparator.

Please clear the confusion with numbers like for example 10 bit 5msps sar adc.

 

[KlausST]

Hi,

Sample and hold is different from comparator.

For a 5MSmpl/s ADC the sample and hold circuit is activated once per sample. Every 200ns.

The comparator must clock for every decoding bit within this sample period. For a 10 bit conversion 10 times in 200ns = every 20ns
That gives a comparator clock of 50MHz.
This is the minimum required timing. In reality from the start of conversion maybe 50 ns are needed for sampling, then the analog value is hold (freezed) and during the remaining 150ns the 10 bits are decoded MSB first. During this 150ns the comparator clocks ten times.

Klaus