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Sampling with MOS transistor and cap

electronics_rama

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Hi All,

I am seeing an issue with the basic circuit used for sampling. Below is the circuit,

1653038370248.png


I am turning off the M1 transistor way before I can turn off the M2 transistor as shown in the diagram. When I simulate this structure, I still see the channel charge going in to the capacitor, changing the voltage at node A and B.

Can I get any help why I see the current flowing through M1 when it is off and changing voltage at node A?



Thanks,
Rama
 

KlausST

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Hi,

you say node A shifts down when "ph1_delayed" is falling.
But at this time ph1 already is LOW, thus M1 is high ohmic .. thus node B is floating.

So it´s quite expectable that A drops.

You don´t see the capacitance of 500f but you rather see the M1 drain capacitance.

Klaus
 

sutapanaki

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The circuit you are showing implies bottom plate sampling. With bottom plate sampling you care about the charge in the capacitor, not about the voltages at A and B. Voltages at A and B will be changing when you turn off M2 because of it's signal dependent charge injection. But the charge in the capacitor should stay pretty much constant because the right side of C doesn't have any resistive path to ground. Does it do that in your simulation?
BTW, for bottom plate sampling you don't really have to turn M1 way before M2. You just need to turn it off slightly before M2, say 100-200-300ps.
 

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