sampling asynch pulse shorter than host clock

[anoop12]

Hi
I am using 50ns clock input for my logic design.
I wish to sample an external pulse ( Asynchronous to host clock) shorter than the clock period. How can I sample it correctly without missing it.

Thanks in advance

 

[Chops211]

The best you can do is use both the rising and falling edges of your clock input to detect the external pulse. Essentially, you are dividing your clock by 2. You cannot guarantee that your design will catch the pulse. Consider delaying the pulse/extending the pulse width using logic.

 

[123jack]

I'd agree with Chops - a pulse stretcher is your best bet unless you could add
an external clock of higher frequency to grab the data and shove it somewhere
before processing.

jack

 

[std_match]

Connect the input pulse to the asynchronous "set" of a register and put a synchronizer after the register. When you have detected the '1' on the output, clock in a '0' in the first register (which will propagate thru the synchronizer).

 

[rca]

as indicate std_match, you can used the signal you want to capture on the reset or set pin or on the clock pin of flop, to capure it.

 

[dincay]

You can use rs-latch or design a simple asynchronous sequential circuit.

 

[Chops211]

If this is being designed using an FPGA, you wouldn't be able to use a latch *for the most part

 

[anoop12]

Thanks guys, its working !!!