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Samples per bit Question

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Aug 29, 2015
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I attached four images.

What do they mean by samples per bits? Is this the inverse of resolution which is bits per sample? But if so, then SPB = 4 => bits per sample = 1/4??


it would be nice if you provide more information than just a couple of pictures.

It seems to be serial communicaton. But what exactely? What bit rate?
Where are the pictures from?


Generaly "4 samples per bit" means, that in the time a single bit is transferred there are four readings of the logic state at the receiver side.
Those four values are digitally filtered to get a more noise immune and thus more reliable bit signal.
Also this ensures a reliable bit value for asynchrounous transfers where two independent clock sources (transmitter, receiver) are involved in the communication. To prevent from interferance effects.


I figured it out.
And yes. What you described is exactly what happens.

Another question.

Consider the following problem:
"Consider a system that uses 8-bit ASCII codes to encode letters. How long will it take to transmit the bit sequence encoding "Good Morning" (not including quotation marks) if we use a bit time of 5 samples per bit, and transmit samples at a rate of 1MHz?"

Ignore the actual solution.
So, I have 12 characters in that string. That means that I need to send 12*8 = 96 bits. So, I send this sequence of 96 bits. And the bit rate is determined by the sampling frequency at the other end, right?

Oooor, I have the sequence of 96 bits. And at the transmitter part, I sample the 96-bit sequence with 5 samples per bit, and I send the 96*5 samples? So, at the receiver, I sample the sequence 5 times per bit.

What do I transmit? When am I doing the sampling?
Do I transmit the 96 bits and do the sampling at the receiver, or do I transmit the 96*5 samples?

*So, at the transmitter, I sample the sequence 5 times per bit.
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I figured it out.

There are two boards facing each other and the transmitting board uses a LED to send bits.
And to send a 1, the LED is switched ON. And it is maintained like so 50 us. And in these 50 us, the other board samples for 50 times with a sampling frequency of 1MHz (so one every microsecond). And the reason for oversampling is reliability, like KlausST said.

So, the sampling is done at the receiving part and 96 bits are sent.

- - - Updated - - -

But my question is this. What is fixed and what is calculated?
Is the sampling frequency fixed and SPB fixed at the receiver side? And thus, the transmitter will have to adjust its bit rate?
Or the bit rate is fixed, and the transmitter if it wants to sample this many times per bit, then it will have to adjust his frequency sampling? Or if it wants a certain frequency sampling then it can only this many timer per bit because the bit rate was fixed?

What is usually fixed?


you didn´t answer the questions about interface.

So I´m not sure if 96 bit is the correct value.
For UART (8N1) you transmit 10 bits per byte, becasue one start- and one stop- bit is added.
So the correct bit count is 12 x 10 = 120.


No special interface. Just two boards facing each other. And a simulation in MATLAB.
The first board receives a bit sequence from the computer. A bit sequence that encodes the characters.
Then the board converts the bit sequence into a continuous time waveform by holding the LED on or off for a certain amount of time called the bit time.
Then the receiving board sees this light and it samples it multiple times per bit for reliability. And thus, it obtains the original bit sequence by averaging those multiple times per bit into a single value. Then it sends the bit sequence to another computer.

Thus, we sent characters from one computer to another computer. This is not long distance communication.


and how do you do syncing?


I'm not sure. They don't say or I haven't seen it.
By the way, I am taking a course on Edx. Hence my questions.

In the video, they do transmit characters from one computer to the other with these boards. In the MATLAB code, there is this communication protocol that the transmitter must satisfy. Maybe here lies the syncing. I'm not sure.

In simple Async ASCII communication in baseband , there is excess bandwidth, so the Receiver generally uses a 16x clock and looks for the leading edge of a start bit then assumes the best time to sample the data once per bit is in the middle using 8 intervals of the 16x clock. THis is how Async data is synced, one byte at a time from the leading edge of the start bit 1>0

If the Stop bit is not a 1 , it is called a framing error, it goes to idle waiting for the next character's start bit or a 1 to 0 transition.

If bandwidth of the channel is not at least twice the bit rate, the probability of error or bit error rate (BER) rises rapidly. Shannon's Law proves the tradeoffs between Signal to Noise ratio (SNR) , bandwidth (BW) and Bit Error rate.

THere are methods to improve SNR by increasing bandwidth and over-sampling but if ambient noise is large, thereby reducing SNR with increasing bandwidth requirements of the channel and receiver, BER degrades. In the ideal channel SNR vs BER yields a straight line in log scales.

Synchronous channels allow deletion of start/stop bits thus save 20% of the time but extra hardware and sync words are needed to allow the Receiver to lock for long data packets and use every bit transition for clock phase error reduction with a design knowing what rate to expect.

Modulation of baseband or ASCII data uses more bandwidth but gives better timing sync error reduction, such as Bi-Phase where clock is XOR's with data used for many wired and wireless communication channels and becomes insensitive to the data patterns. If Bandwidth is expensive such as in mobile phones, time compression is performed by assigning a larger number of bits to an analog value of amplitude and phase rather than simple binary. So 12 bytes can be sent in the same BW channel with compression rates that increase with the SNR available, such as 256 levels.

So to answer your question about how many samples per bit, depends on the channel bandwidth (BW) , the Receiver BW and detector type ( integrator or centre sample) and the transmitter BW used and distortion of group delay vs f if there is bandwidth limiting in any part or special filtering added.

In the simplest case with excess bandwidth like all UARTs Data is sampled at 16x clock for start bit then only centre sampled once per bit into a register byte then repeats for next character. 16 BYTE UART buffers allow consecutive bytes without loss, otherwise some latency or delay between words are expected so the Receiver does not miss and data sent. Thus 1 start bit (always =0) 8 data bits and 1 stop bit (always=0) means 10 bits * 12 bytes * 1us per bit = 120us. up to 16 bytes, then delay depends on handshaking of the serial port for flow control or a special character of data call XON, XOFF.

1Mb/s is pretty fast so you can't really use an LED to transmit the data as it does not have the required BW due to LED diode capacitance, unless special low capacitance IR diodes are used such as found in IRDA2 specs.

Keep in mind ASCII serial ports on uC , when converted to RS232 are different voltages and also inverted polarity ( at both ends) by definition.

I have no doubt this answer will raise more questions.

I don't really know if you responded my question or not.

The bit time is equal to the number of samples per bit times the sampling period.

Thus, if I choose a bit time, then the receiver must adjust its number of samples per bit and sampling period in order to match this bit time. He can also trade-off between number of samples per bit and sampling period so that bit time is constant.

Or, If I choose a certain sampling frequency and a certain number of samples per bit, then the transmitter will have to adjust his bit time to match the requirements of the receiver.

And my question is: usually, who really decides first? which quantity is fixed? the bit time? or the sampling frequency and SPB?

My guess is that the transmitter sets the sampling frequency and the SPB, while the receiver will have to adjust its bit time.

Maybe the answer lies into your response. But its too advanced for me. I've just started learning digital communications.

Like I said UARTs usually have 16x clocks and then sample only once per bit in middle, since the channel has excess BW and fast rise time compared to bit period.

Coherent synchronous radios do the same except integrate all the energy of the bit to determine at the end of the bit, if a 1 or 0.

If not using these methods then oversampling and averaging improves SNR only by square root of the number of samples, so Shannon's Law dictates, you choose the filter, detector and discriminator method required to obtain a reliable signal over the designated path loss and resulting SNR.

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