Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Sample and hold circuit tester

Status
Not open for further replies.

Lutgeyara

Newbie
Joined
Feb 3, 2021
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
8
Hello
I am rying to creat a sample and hold tester using veriloga code. But i am confused hoe to develop this using timer? Here is some details of the code but i confused how to develop this. I am new in this section.

Code:
module Sh_tester (sh_inp, sample, avdd, in1, in2);

input in1, in2;
output sh_inp, sample, AVDD;
electrical sh_inp, sample,AVDD, in1, in2;

parameter real avdd_value = 5.0;
parameter real period = 100n; //sampling period
parameter real A = 1.0;
parameter real time_tol = 10p; //call for timer every 10p
parameter real td = 0.0; //delay from sampling to output
parameter real trf = 1n ;
parameter real tpd = 0;


real ts, var1, var2;

//file identifier

integer fid;

analog begin
    @(initial_step) begin
        fid = $fopen ("~/cdc/ece595/results/sample_hold_tester.pdf");
    //    f = 1/period  ;
    end
// close file
    @(initial_step) begin
        $fclose (fid);
    end

@ (timer(0, period, time_tol)) begin
        var1 = 0;





// supply voltages
    V(AVDD) <+ avdd_value ;

endmodule
 
Last edited by a moderator:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top