Sample and Hold Circuit. explainary is need ! Urgent!

[AlvinTan]

Hi,

I need help to understand the circuit to be implemented in my project. Can someone provide me guidance to understand how this sample and hold circuit works?

Thanks.

---------- Post added at 18:32 ---------- Previous post was at 18:30 ----------

Sorry... I need two posts before I can post the schematic diagram.

 

[ckshivaram]

http://www.eecg.toronto.edu/~kphang/papers/2001/jwong_SH.pdf

**broken link removed**

 

[AlvinTan]

Hi,

This is the schematic diagram for the sample and hold circuit in the document. I need help to understand the circuit to be implemented in my project. Can someone provide me guidance to understand how this sample and hold circuit works?

Thanks.

 

[chuckey]

A switching wave comes in on J115, this is differentiated by c115/R127 and the positive going edge removed by D103, the resulting negative going spike goes through U107c so is applied as the gating pulse to V108. The output on J116 is the input waveform, where the sampling point is sat at earth potential.
Frank

 

[FvM]

For the internal circuit of LF398, consult the datasheet **broken link removed**
The timing circuit provides a 7 us sampling pulse at the negative edge of the control input waveform. It's a special function of the specific circuit, not generally necessary for S&H operation. You have to know the purpose of the circuit to understand why it's done this way.

 

[AlvinTan]

points noted. appreciated with much thanks.

Regards
Alvin