sample and hold circuit design

[thirupathi reddy]

for the transmission gate type of sample and hod circuit design, the widths of both the n-channel and p-channel transistors must be same ? or width of p-ch = 2.5 times the n-ch transistor width?

 

[sm_rashtyan]

hi
In s&h circuit , the W/L of transistors is greater than 1 or 2.5 like the digital circuits. In this kind of circuits W/L is depended on sampling frequency, accuracy ,amount of cap and ...
best wishes

 

[jiangxb]

the w/l of pmos is 2~3 times larger than that of nmos for relative plat on-resistance, i.e. small distortion.

 

[wael_wael]

in fact from my small experience i can till u is depend the mos model u r using, i have designed one and pmos two times nmos, but u have test the SFDR after u adjust the w/l, and after many times u can find the best w/l
regards

 

[jeffsky520]

That w/l of pmos is 2~3 times larger than that of nmos for relative plat on-resistance is one of design considerations, but charge injection is another key issue should be mentioned.

 

[jnuhope]

in fact from my small experience i can till u is depend the mos model u r using, i have designed one and pmos two times nmos, but u have test the SFDR after u adjust the w/l, and after many times u can find the best w/l
regards

How do you run SFDR? What kind of tools do you use to run it? Thanks in advance!

 

[wael_wael]

i am using TSPICE simulator, there is tool for SFDR, after u do the transient analysis u can do SFDR analysis for the transient output. check ur simulator first if dont have go to matlab, let me know if u cant do it,
best regards