As far as I understand, in order to simulate post-PAR model, I should compile SIMPRIM library. And to do that, I should choose the simulator I'll be using. And Isim is not in the list.Sure you can. I've been doing far too much post place & route simulation lately. And in Isim (13.1) no less. So what makes you think you can't?
(* ASYNC_REG = TRUE *) reg my_async_stuff = 1'b0; // this will help help simulate your asynchronous logic
My thoughts exactly.So judging by the fact that you get a running simulation I'd say you have the libraries alright.
And then again, it was simulating way too fast. Like 5 times faster than corresponding RTL model does.
yes, I got what you meant the last time. Just not before that.By "simulation running too fast" I meant exactly what I said
Nope...Maybe different settings?
OK, I got it.
It is only now that I have noticed a warning (well, a hundred of warnings):
" <x_xor2> remains a black-box since it has no binding entity.". And similar for other components.
And I think I've found source files for all the primitives.
One thing I really hate about ISE - it's really bad at handling librarys with large amount of files...
Now I have no warnings while compiling and elaborating, and simulation runs slowly (just as I like:-D), but again - nothing on output ports of UUT...
Yep. I initially included some, but not all (really don't understand how could it happen).You needed the ones in "ise_124/ISE_DS/ISE/vhdl/src/simprims/" or something like it?
Clock signal (and some other signals) is generated by testbench, it's simple plain VHDL. It's UUT is post-PAR model, to which testbench feeds input signals (clock included). And outputs of UUT are U's.Nothing, not even a clock signal or something like that?
Yep. I initially included some, but not all (really don't understand how could it happen).
Clock signal (and some other signals) is generated by testbench, it's simple plain VHDL. It's UUT is post-PAR model, to which testbench feeds input signals (clock included). And outputs of UUT are U's.
I'm really stupid today. Now I got it, thanks for the idea.That's what I meant by "now even clock?" since I would expect at least something like that to arrive in one piece to the UUT module...
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