# Same channel length but different technology

#### Junus2012

##### Advanced Member level 4
Dear friends,

Suppose I use to design with 0.35 µm technology and using a channel length of 1 µm, that is about 3 times minimum length and with VDD = 3.3 V
Now I build the circuit with 180 nm technology and still using a channel length of 1 µm (now 5.5 times minimum length) and suppose the same VDD = 3.3 V

Will both the circuits will have the same channel length modulation effect? or the latter one should be better because it is 5.5 bigger than the minimum although both having the same absolute length.

In the other way I would say is 3 times 180 nm is identical in performance to the 3 times 0.35 µm technology

Thank you

#### Dominik Przyborowski

##### Advanced Member level 3
Now I build the circuit with 180 nm technology and still using a channel length of 1 µm (now 5.5 times minimum length) and suppose the same VDD = 3.3 V
For core devices in 180nm maximum supply is 2V.
Will both the circuits will have the same channel length modulation effect? or the latter one should be better because it is 5.5 bigger than the minimum although both having the same absolute length.

In the other way I would say is 3 times 180 nm is identical in performance to the 3 times 0.35 µm technology
General answer is no.
Different technology means at least different doping density/profile, insulator thickness, junction depth.
All these parameters can result with differences in DIBL, carriers scattering caused by vertical field and also channel modulation, current gain factor - in one word - different characteristic for the same dimensions.

Junus2012

### Junus2012

points: 2

#### Junus2012

##### Advanced Member level 4
Dear Dominik,

There is one thing I couldn't understand,
Let us speak for general IC design (not high speed), it is recommended to work at least twice to triple the minimum channel length, let us agree on the ratio of three as a common solution . So now with my technology 0.35 µm I would design with L = 1 µm, and I get very excellent results

If we go back in time to older technology of 1 µm, people were using 2 to 3 µm.

Here is the question, if the 1 µm is fine for me, why people at the technology of 1 µm use higher,

is the selected channel length is absolute or relative to the technology min length

Thanks

#### Dominik Przyborowski

##### Advanced Member level 3
Let us speak for general IC design (not high speed), it is recommended to work at least twice to triple the minimum channel length, let us agree on the ratio of three as a common solution . So now with my technology 0.35 µm I would design with L = 1 µm, and I get very excellent results
It was a common "rule of thumb" introduced in early sub-micron nodes (<1µm) related to observable that time short channel effects.
If we go through process parameters, we can see the reason.
 Parameter/Process 2.5µm 1.6µm 0.7µm 0.35µm 0.13µm tox (nm) 50 25 17 7 2 Vdd (V) >5 5 5 3.3 1.2 NMOS Avt (mV·µm) 30 20 15 10 14

1. Effect of vertical electric field
If we look on drain current equation we find parameter called current gain factor K defined as product of mobility and gate capacitance µ·Cox.
However, due to electrical field in channel, both vertical caused by V_GS and horizontal caused by V_DS, K is process and bias dependent.
Quasi-empirical formula for effective K value is following (for NFET):
$K_{eff} \approx \frac{\mu C_{ox}}{\left [ 1+\theta (V_{GS} - V_{Th} ) \right ] \sqrt{1+ \left ( \frac{V_{DS}}{L E_C} \right )^2}}$
$\theta \approx 10^{-7}/t_{ox} (V^{-1})$ is empirical parameter related to vertical field, while Ec=0.8 (MV/m) is "critical" electric field value for electrons - for this value of electrical field, velocity of electrons in silicon saturates, so linear relation between electron velocity and accelerating electron field is broken. V_DS in this relation is voltage across channel, so it is Vdssat for saturated mosfet and V_DS for linear one. The most important effect here is related to horizontal field and channel length.

Now, lets look how K_eff is degraded in mentioned process with $V_{GS} - V_{Th} = 0.2 V$ and minimum width.
 Process 2.5µm 1.6µm 0.7µm 0.35µm 0.13µm $\sqrt{1+ \left ( \frac{V_{DS}}{L E_C} \right )^2}$ 1.005 1.012 1.062 1.23 2.168

Due to velocity saturation, degradation in min length mosfet transfer characteristic became much stronger below 1µm.

2. DIBL
Another phenomena influencing submicron transistors is drain induced barrier lowering. V_DS decreasing potential barrier for carriers inside the channel to overcome - what is simply visible as decreasing the V_Th with increasing V_DS.
$\Delta V_{Th} \propto V_{DS} e ^{\frac{\lambda}{L}}$

where $\lambda$ is quasiempirical process constant (called characteristic length).
Now, if we add V_DS caused shift in V_Th to output characteristic (Id=f(V_DS)), we can get higher slope than for constant channel modulation.

3. Channel length modulation
Channel length modulation is also bias and dimension dependent.
$\lambda_m \propto \frac{1}{L} \frac{1}{\sqrt{V_{DS} - V_{GS} + V_{Th}}}$

The effect of points 2 and 3 on output characteristic is strong enough to decrease r_ds by factor of 5 with decreasing L from 1µm to 0.3µm (and much more beyond).

4. Noises
Thermal noises of long channel mosfet are $$\overline{i_n^2} = 4 k T \gamma_n g_m$$ , where $\gamma_n$ is within range of 0.5 - 1 depending to biasing. In case of velocity saturation (point 1) thermal noises expressed by Klaassen-Prins equation are modified to:
$\overline{i^2_{n_{ch}}}=\frac{4 k T}{I_D L_{c}^2}\int_{V_0}^{V_L} g_c^2(V)dV$, where g_c is channel conductance.
It is clear that noise is boosted for short channel devices. For channels below 100nm situation is even worse due to very high electric field in channel and strong carrier scattering caused by it (it can be shown by applying free electron model to transport process).

5. Matching
Mismatch parameters are scaling nicely with square root of t_ox (until introducing new features in the process), however the mosfet area for certain accuracy were large enough to force usage of non-minimum length, especially for current sources (requirements for strong inversion)

6. Summary for sub-micron CMOS
Going below channel length of 0.5µm (lets make convention 0.3µm for moderate inversion) results with visible velocity saturation effect and DIBL, which are responsible for drop in transconductance, channel conductance and thus intrinsic gain (it can be found drop of 10-20dB by changing L from 1µm to L_min). All this increases noises as well, so this is the main reason why we have common opinion of using 2-5 times of Lmin - what for 90 - 250nm processes results with L=0.5µm.

7. Epilogue
Decananometer CMOS start to suffering on other issues related to junction depth and diffusion effects making transistor almost opens for V_GS=0, so to overcome this "short channel effects" new features like halo implants start to be added. Also t_ox in order of 1nm results with gate leakage in order of µA/µm². So, the last CMOS process - high-K 28nm is a guy in which to achieve 60dB gain, OPAMP need two gain boosted cascode stages, while for good matching current sources has to be build as stack of several Lmin units (halo implants makes A_Vth strongly bias and length dependent). Also, noises can be higher by factor of 3-5 than expected from classic relation.

Fortunately, in "beyond CMOS" processes transistors performing perfectly, with lower noises, higher gain and superior matching as long as they are small (what might be suspicious at beginning).

Junus2012

points: 2

### MahmoudHassan

points: 2

#### Junus2012

##### Advanced Member level 4
6. Summary for sub-micron CMOS
Going below channel length of 0.5µm (lets make convention 0.3µm for moderate inversion) results with visible velocity saturation effect and DIBL, which are responsible for drop in transconductance, channel conductance and thus intrinsic gain (it can be found drop of 10-20dB by changing L from 1µm to L_min). All this increases noises as well, so this is the main reason why we have common opinion of using 2-5 times of Lmin - what for 90 - 250nm processes results with L=0.5µm.

Dear Dominik,

Thank you very much for your explanation,

It was great way you explained each section,

I understand from it that below 1 µm or even below to 0.5 µm the problems of the short channel effects degrade most of the design performance.

Hence you stated for 90 nm we need a factor of 5 and for 250 nm you used factor of 2, which means that if I am using 1 µm or hiogher then I don't need to multiply the channel length (except if someone is needing for high gain or low noise amplifier, etc)

So that is indeed what I needed to know, the multiplication is required to approach the 0.5 µm, it is not a relative multiplication, rather it is needed to reach absolute value.

What about people working in 60 nm, they need by this way to multiply it with 9, what about 28 nm?
If we still multiply to approach higher channel length, then only the digital part of the IC will make use and benigit from the advance CMOS technology

Thank you very much

#### Dominik Przyborowski

##### Advanced Member level 3
which means that if I am using 1 µm or hiogher then I don't need to multiply the channel length
You may see higher r_ds for L>1µm, but it is not scaling linearly (it means, L=2µm has no 2×r_ds of L=1µm, rather 10% more).

What about people working in 60 nm, they need by this way to multiply it with 9, what about 28 nm?
In such processes transistors intrinsic gain is in order of 2-10 and due to halo implants even long 1µm device has poor r_ds, so it is all.
if you need 60dB open loop gain you are going to 2 stage gain boosting (both stages) and/or negative conductances.

If we still multiply to approach higher channel length, then only the digital part of the IC will make use and benigit from the advance CMOS technology
Speed is a benefit. Ft in 65nm is around 150GHz. The switching speed is GHz too. The mosfet transfer characteristic in decananometer processes is still not bad. It deteriorates for strong inversion, but with Vdd of 1V, no one is interested in strong inversion.

In process older than 180nm, the choice for ADC was usually pipeline as the best trade-off between speed and power.
In such decananometer process with poor intrinsic gain, but higher speed, pipeline lost for capacitive SARs, because it was finally possible to achieve moderate number of bits with tens MHz sampling (and save a lot of power in comparison to pipelines).

Junus2012

points: 2