Safely transfer the data

[sun_ray]

Suppose a two bit data is coming from one clock domain and needs to be transferred to another clock domain. Suppose the data can change in every clock at the originating clock domain. Here there is no finite burst size of the data as usual. How can we safely transfer the data?

Regards

 

[FvM]

"Safely transfer" means exactly what in this case? Consistency of the two bit data word?

Is the receiving clock rate guaranteed to be higher or equal to the sending?

 

[KerimF]

I guess there must be a starting pattern (simple or complex) for each packet of data. This pattern synchronizes the two domains (their clocks), for a period of time in the least.

 

[sun_ray]

"Safely transfer" means exactly what in this case? Consistency of the two bit data word?

Is the receiving clock rate guaranteed to be higher or equal to the sending?

Safely transfer means the data in the originating clock domain should not be destroyed in the receiving clock domain. Hope this clarifies your question. Please let me know if it needs more clarity.

We can think of two cases for this problem
(a)The clock frequency for the receiving clock domain can be higher or equal to the frequency of the originating clock domain.
(b) The clock frequency for the receiving clock domain can be lesser or equal to the frequency of the originating clock domain.


CAN YOU PLEASE REPLY TO MY QUESTIONS IN THE THREAD OF MULTIPLIER VERILOG OPERATOR AND MULTIPLICATION?

---------- Post added at 10:16 ---------- Previous post was at 10:12 ----------

I guess there must be a starting pattern (simple or complex) for each packet of data. This pattern synchronizes the two domains (their clocks), for a period of time in the least.

kERIMf

I did not understand what you are trying to say. Here there is no particular pattern at the starting. How are you thinking of doing this with a starting pattern?

 

[KerimF]

Sorry, it seems I misundestood your problem...
Please forget what I wrote, I was just talking about the way I transfer data (one bit, 1-wire) without a continous burst signal for data/clock (like 25% and 75% pulses for 0's and 1's).

 

[FvM]

Safely transfer means the data in the originating clock domain should not be destroyed in the receiving clock domain. Hope this clarifies your question. Please let me know if it needs more clarity.

I think the term data word consistency is asking for a more specific detail. Let me assume, that you need word consistency.

We can think of two cases for this problem
(a)The clock frequency for the receiving clock domain can be higher or equal to the frequency of the originating clock domain.
(b) The clock frequency for the receiving clock domain can be lesser or equal to the frequency of the originating clock domain.

In the second case, part of the data will be necessary lost and some synchronization methods are excluded.

To suggest a simple synchronization method, decode the 2 bit to 4 bit one-state-hot and re-encode it at the receiver side after double registering the data. In the special case of receiving no bit set, keep the previous state.

CAN YOU PLEASE REPLY TO MY QUESTIONS IN THE THREAD OF MULTIPLIER VERILOG OPERATOR AND MULTIPLICATION?

I answered it as far I see a reasonable answer. I'm sure others will supplement my post if they consider it necessary.

 

[sun_ray]

I think the term data word consistency is asking for a more specific detail. Let me assume, that you need word consistency.



In the second case, part of the data will be necessary lost and some synchronization methods are excluded.

To suggest a simple synchronization method, decode the 2 bit to 4 bit one-state-hot and re-encode it at the receiver side after double registering the data. In the special case of receiving no bit set, keep the previous state.


I answered it as far I see a reasonable answer. I'm sure others will supplement my post if they consider it necessary.

What do you mean by "some synchronization methods are excluded."

What do you mean by " In the special case of receiving no bit set, keep the previous state."

Can you please provide a solution for case (a) ?

 

[FvM]

Can you please provide a solution for case (a) ?

I suggested decode to 1-out of-4 (one state hot).

What do you mean by "some synchronization methods are excluded."

E.g. DC FIFO, because it would overflow.

 

[sun_ray]

E.g. DC FIFO, because it would overflow.

What do you mean by 'DC'?

You wrote "In the second case, part of the data will be necessary lost and some synchronization methods are excluded."

What do you want to mean by this "In the second case, part of the data will be necessary lost and some synchronization methods are excluded." Which synchronization method can work here?


What do you mean by "What do you mean by " In the special case of receiving no bit set, keep the previous state."?

Regards

 

[FvM]

I thought "DC FIFO" (domain crossing FIFO) to be a known technical term.

You presumed that the data is changing every clock cycle of the sending domain. So in case b, data words are necessary lost, isn't it?

"In the special case of receiving no bit set, keep the previous state" is said related to re-encoding one-state-hot. If you think about the solution in detail, you'll realize that this can happen.

 

[sun_ray]

I thought "DC FIFO" (domain crossing FIFO) to be a known technical term.

You presumed that the data is changing every clock cycle of the sending domain. So in case b, data words are necessary lost, isn't it?

"In the special case of receiving no bit set, keep the previous state" is said related to re-encoding one-state-hot. If you think about the solution in detail, you'll realize that this can happen.

The one hot encoding is not grey encoding. In a grey encoding the data at the output of the synchronizer either changes or remains at the earlier value. So still there can be issue with transferring the data by doing one hot encoding.

Regards

 

[dcreddy1980]

For the two scenarios mentioned as "a" and "b", data will be lost.

If we chose a FIFO of certain depth, and if we dont know how the reciever is gonna take the data out from the FIFO, FIFO will be full after a period of time since you are continously sending new daya every clock cycle.

 

[FvM]

The one hot encoding is not grey encoding. In a grey encoding the data at the output of the synchronizer either changes or remains at the earlier value. So still there can be issue with transferring the data by doing one hot encoding.

You can achieve a similar behaviour as with grey encoding when re-encoding the one-state hot signal in a suitable way. When two bits are set, you you can select just one of it (priority encoding), if none is set, you keep the previous state.

For the two scenarios mentioned as "a" and "b", data will be lost.

Case b is clear, for case a, I don't think that data is lost. The meaning of the data hasn't been clearly stated, so you need to guess about it.

 

[sun_ray]

Case b is clear, for case a, I don't think that data is lost. The meaning of the data hasn't been clearly stated, so you need to guess about it.

The data is a two bit data which is coming from a digital system. The data can change in every clock cycle at its own originating domain. Is it clear now what the data is? You shoud not assume about the data. The data can take any value between 0 to 3.

You can achieve a similar behaviour as with grey encoding when re-encoding the one-state hot signal in a suitable way. When two bits are set, you you can select just one of it (priority encoding), if none is set, you keep the previous state.

I am stating about grey encoding of the one hot encoded value and nnot of the 2 bit data that is coming. When this one hot encoded data is sent to the new clock domain there can be issues as this one hot encoding is not a grey encoding and hence more than one bit can change once the one hot encoded value changes.


Regards

 

[FvM]

In my view, the nature of the data matters when designing synchronization. I see at least two cases:

- The 2-bit value represents a state information without defined timing. It can be sampled in the receiving domain at different rates without issues. If f2 < f1, it may happen that a state only present for one cycle will be ignored at the receiving side. If the sample point coincides with a data change, synchronization has to assure that either the old or the new value is read, but no other bit combination.

- The 2-bit value is part of a serial data stream that should be received as a correct sequence. The synchronizer must implement a handshake mechanism to assure that each word is read exactly once. The average receive rate must be equal to the send clock. Consequently, this case requires a clock transmitted with the data or a clock recovery mechanism.

A domain crossing FIFO is the standard means to handle the second case. It can be used for the first case, too.

The suggested one-state hot coding is intended as a simplified method to handle the first case (asynchronous state information). I also mentioned a way to handle the re-encoding of inconsistently transmitted codes.

Asuming the binary data changes from "00" to "11" and one-state-hot from "1000" to "0001" respectively. Then "1001" or "0000" can be seen as transient values.
To resolve these "illegal" codings, you can refer to the previous state.