Running VHDL files in Cadence environment

Hi, i was wondering if anyone has had experience running VHDL files in Cadence environment. What I meant is that, you wrote some VHDL file in design.vhd and then supposingly import into cadence and it generate entity and structural and a symbol. This is as far as I got, but then when I try to simulate it, I encounter 2 problems:

1) I am not sure what my stimulus are because VHDL is digital and if I use Analog Environment, everything is analog.

2) It keeps saying something like this "ERROR: Netlister: unable to descend into any of the views defined in the view list: "spectre cmos_sch cmos.sch entity structural schematic veriloga ahdl" for instance I4 in cell trial.", but at least the entity and structural cellview are there for instance I4.

Am I doing something wrong?

Thanks

cadence analog stimulus vhdl

Use Cadence LDV.

entity symbol cadence vhdl

LDV was no longer supported by Cadence. It was replaced by Incisive.

vhdl import to cadence packages

spweda said:

LDV was no longer supported by Cadence. It was replaced by Incisive.

Click to expand...

LDV is called IUS in the new version

Re: Run VHDL in cadence

Hi, I did install IUS package, but I can only seem to do Verilog in AMSDesigner but not VHDL, it says it cannot descend to the cellviews that I specific. Since VHDL has views like "entity" and "behavior", I bind one of my block to behavior since it IS behaviorally defined, but it says it cannot descend into the behavior cellview. The way I generate the behavior view is to use VHDL-In

Thanks for all the help