Aug 3, 2017 #1 L liaquat95 Newbie level 2 Joined Jan 25, 2017 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 15 Hi all I am trying to run the inverter.sp file given by the website https://bsim.berkeley.edu/models/bsimsoi/ Code: *Sample netlist for BSIMSOI -- Tanvir Morshed 2010 *Inverter DC .option abstol=1e-6 reltol=1e-6 post .hdl "bsimsoi450.va" .include "modelcard.bsimsoiVA.pmos" .include "modelcard.bsimsoiVA.nmos" Vpower VD 0 1.5 Vgnd VS 0 0 Vgate Gate 0 0.0 xn0 VS Gate Out VS nmos1 W=10u L=0.18u xp0 VD Gate Out VS pmos1 W=20u L=0.18u .dc Vgate 0 1.5 0.05 .print dc v(out) .END I have included the va and other nmos and pmos files in the same directory but still I have facing the issue
Hi all I am trying to run the inverter.sp file given by the website https://bsim.berkeley.edu/models/bsimsoi/ Code: *Sample netlist for BSIMSOI -- Tanvir Morshed 2010 *Inverter DC .option abstol=1e-6 reltol=1e-6 post .hdl "bsimsoi450.va" .include "modelcard.bsimsoiVA.pmos" .include "modelcard.bsimsoiVA.nmos" Vpower VD 0 1.5 Vgnd VS 0 0 Vgate Gate 0 0.0 xn0 VS Gate Out VS nmos1 W=10u L=0.18u xp0 VD Gate Out VS pmos1 W=20u L=0.18u .dc Vgate 0 1.5 0.05 .print dc v(out) .END I have included the va and other nmos and pmos files in the same directory but still I have facing the issue
Aug 4, 2017 #2 D dick_freebird Advanced Member level 7 Joined Mar 4, 2008 Messages 8,968 Helped 2,333 Reputation 4,683 Reaction score 2,515 Trophy points 1,393 Location USA Activity points 71,456 "The issue" being what, exactly?