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Running Dhrystone on Oregano IP core

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kinks

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Hey Guys ,



I am working on design a of a low power microcontroller project and I needed to run Dhrysone on my core which is a 8051 Oregano Systems core.

Can someone help me out in running the Dhrystone analysis for the Oreagno core. Is there an method to do this using Keil and using the Rom.vhd file of the Oregano core in Modelsim.

I tried this process by compiling the code in Keil and converting the generated HEX file (after project Build ) to
1.dua and loading the contents of the .diua filr into the ROM.vhd file and running the Simulation. I used a writetofile.do script which generates a log file which should match with the contents of the 2.dua file(1.dua nd 2.dua are different) genrated after running the Dhrystone code in Keil in debug mode and saving it in .hex mode and convertying it to .dua.
The log file and the 2.dua file match for small ASM code s and small C codes but they don't match for Dhrystone and other larger codes like Factorial etc.


Someone please help me in running Dhrystone on the Oregano Core.

Thanx in advance
 

kinks

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Guys,

Someone please help me out in this. I need to do this task very urgent. How do I run Dhrydtone 1.1 benchmark for Oreagno 8051 core
 

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