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RTL/ Verilog validation

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zahrein

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HI i have some questions regarding the verilog validation. I have known that the Behavioural model is just checking the functionality of the circuit.
Since im working in SRAM, the customer asked me to validate the timings specified in the RAM document? Is this part of RTL validation or is it related to circuit validation.

The whole question, what is the coverage for RTL validation. How to distinguish between the ckt and RTL validation.
 

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