RTL simulation using memory lib

[wind7312]

ncverilog +notimingchecks

Hi,
I do RTL simulation using memory verilog lib,do the $setuphold( )is needed?
The result is X state.

best regards

 

[spauls]

notimingcheck vcs

I am not sure which tool you are using for reading .lib for simulation.
if you are able to use .lib than it is not required.

 

[aji_vlsi]

ncverilog uselib -y -v

Hi,
I do RTL simulation using memory verilog lib,do the $setuphold( )is needed?
The result is X state.

best regards

If you do RTL sim and don't care about timing checks, use +notimingchecks with VCS/VXL etc.

Which tool do you use?

Ajeetha, CVC
www.noveldv.com

 

[lightcloud]

ncelab notimingchecks

Hi,
I am use ncverilog,how to set parameter?

Added after 26 minutes:

IN ncverilog should add the notimingcheck?

 

[aji_vlsi]

using memorylib;

Hi,
I am use ncverilog,how to set parameter?

Added after 26 minutes:

IN ncverilog should add the notimingcheck?

ncelab -notimingchecks

If you use one step ncverilog, then it is +notimingchecks I believe, check their cdsdoc for more

HTH
Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/