RTL for synthesis for loops

[sun_ray]

Are the following verilog loops synthesizable for both FPGA and ASIC?

(i) for loop.
(ii) while loop
(iii) forever loops

Will there be any issues of using the above loops even if they are synthesizable?

 

[ranger01]

definitely forever isn't synthesizable !!!!. "for" loop with a constraint is synthesizable. These answers are for ASIC but I am not aware of FPGA synthesis.

 

[FvM]

HDL constructs are synthesizable if they can be mapped to existing hardware by the used synthesis tool.

Looping statements are a general language element that don't depend on specific hardware features, except for finiteness of resources. In so far I don't see a difference between ASIC and FPGA implementation.

IEEE 1364.1, the IEEE Standard for Verilog Register Transfer Level Synthesis attempts to define a Verilog subset that is commonly understood by synthesis tools. It restricts the looping statement support to for loop statements (both procedural and function) and specifies this additional constraint: "Loop bounds shall be statically computable for a for loop"

IEEE 1364.1 recommondations aren't strictly implemented by all synthesis tools, but I expect that all tools understand for loops. The important point is that the loop bounds respectively the number of iterations must be known at compile time. You can also design while loops that fulfill this constraint, but because the criterion is less obvious, 1364.1 apparently opted against it. It's of course possible that a tool implements features beyond the requirements of the standard.

forever is only used in special constructs that aren't relevant for synthesis as far as I understand.

 

[henry_0726]

The for loop is synthesizable. the forever and while loop unsynthesizable.

 

[sakthikumaran87]

For loop is the only synthesize loop, but it is always wise not to use loops in Verilog as timing closure will be an issue.

 

[FvM]

but it is always wise not to use loops in Verilog as timing closure will be an issue.

Makes no sense if stated that generally. Looping constructs are enrolled to parallel logic during synthesis. In some cases, they don't affect timing at all, e.g. when independent logic is created for each bit of a vector. In other cases, the output of one iteration is an input to the next, using blocking assignments and propagation delay is multiplied. But it may be still intentional. By changing the construct a bit, you are inferring registers and fast pipelined logic.

In other words, looping constructs are serving a purpose in synthesizable HDL. You need to know what you are doing.

 

[sun_ray]

By changing the construct a bit, you are inferring registers and fast pipelined logic.

Can you please provide examples of RTL where for loop is being used to construct register and also fast pipeline?

Regards