RTL for Clock divider circuit

[Sree Harsha M]

Hello,
I need to model a clock divider clock with the following pins and functionality:

1. input iclk -
This pin is input clock . It can be any one of 10Mhz, 20Mhz, 30, 40....160Mhz.
2. input [3:0] iclk_div_sel
The input given to this pin is dependent on the frequency given to iclk i.e,
if 10Mhz is given on iclk, then iclk_div_sel should be 0000,
if 20Mhz is given on iclk, then iclk_div_sel should be 0001,
if 30Mhz is given on iclk, then iclk_div_sel should be 0010,
if 40Mhz is given on iclk, then iclk_div_sel should be 0011,......AND SO ON.....

if 160Mhz is given on iclk, then iclk_div_sel should be 1111,

3. output oclk
This is output clock. Irrespective of the above mentioned frequencies on iclk...this oclk should be 10 Mhz


Could anyone suggest how to proceed on this? Or is this feasible with this pins or any extra pins are required to achieve this??

Thanks in advance,
-Harsha

 

[TrickyDicky]

I assume this is some kind of homework assignment that I assume would want you to use a counter, because in a real life design you would never do anything like this.
What have you done so far, and what problems are you having with it?