[SOLVED] RTL Compiler : Net has unmapped pin(s)

[phutruan]

Hello,

I'm trying to synthesize an adder. The Verilog source code is very simple (assign sum = in1 + in2)
To achieve maximum speed, I did "set_max_delay 0". During synthesis, RTL compiler informed "Net has unmapped pin". However, synthesis still succeeded. Then I checked the mapped netlist file. Surprisingly, there was no unmapped pins? Anyone, please tell me why.

 

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did you account for the bit growth of sum when you add in1 + in2? The tool is likely reporting that it dropped the carry out of the addition.