RTL compiler insert certain combinational delay

[makanaky]

Hi,

Is there a command in RC to insert certain delay between 2 signals ?

 

[jbeniston]

Not that I know of. You can manually insert buffer cells. But obviously you will get a variable delay.

 

[sharath666]

You cannot accomplish that with a synthesis tool. You either achieve it in simulation by using #delays or in the real chip using buffers or invertor pairs

 

[rahul.achates]

So far I dont know the command , If you get to know then dont forget to publish here.

May be you can play with set_min_delay/set_max_delay on the source signal .. tool may add some buffer to achieve the constraint on that net/pin.

 

[rca]

There is a command set_data_check, which add a constraint between two pins. The constraint could be different for setup and hold, like this:

set_data_check -from U6/DAT -to U6/EN -setup 1.0
set_data_check -from U6/DAT -to U6/EN -hold  1.0

- - - Updated - - -

You could constraint to have a specific delay between your two destinations pins if the source pins comes from a flop, the tool should add delay to respect the constraint at the destination pins.

 

[makanaky]

thanks all for trying to help , I found command called "path_delay -from x -to y " , it modifies the SDC

but this is not reflected in SDF , is there any method to view this on simulation ?