Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

RTL Code , Verilog, VHDL?

Status
Not open for further replies.

digi001

Full Member level 5
Joined
Apr 5, 2011
Messages
244
Helped
22
Reputation
44
Reaction score
21
Trophy points
1,298
Activity points
2,904
I understand what Verilog and VHDL languages are, but what exactly encompases the term RTL Code?

Is RTL Code just the synthesizable portions of Verilog and VHDL? Or is RTL code its own type of language?
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,068
Helped
2,078
Reputation
4,173
Reaction score
2,031
Trophy points
1,393
Activity points
39,145
RTL stands for Register transfer level. Basically code that describes the behaviour of a synthesisable circuit. This could be any language. So any code in any language that is synthesisable is RTL code.
 

digi001

Full Member level 5
Joined
Apr 5, 2011
Messages
244
Helped
22
Reputation
44
Reaction score
21
Trophy points
1,298
Activity points
2,904
Ok, so for verilog code:

Code:
 always @ (posedge clock or posedge reset)
  if (reset) begin
   gnt_0 <= 0;
   gnt_1 <= 0;
  end else if (req_0) begin
    gnt_0 <= 1;
    gnt_1 <= 0;
  end else if (req_1) begin
    gnt_0 <= 0;
    gnt_1 <= 1;
  end


  // Testbench Code Goes here
  module arbiter_tb;
  
  reg clock, reset, req0,req1;
  wire gnt0,gnt1;
  
  initial begin
    $monitor ("req0=%b,req1=%b,gnt0=%b,gnt1=%b", req0,req1,gnt0,gnt1);
    clock = 0;
    reset = 0;
    req0 = 0;
    req1 = 0;
     #5  reset = 1;
     #15  reset = 0;
     #10  req0 = 1;
     #10  req0 = 0;
     #10  req1 = 1;
     #10  req1 = 0;
     #10  {req0,req1} = 2'b11;
     #10  {req0,req1} = 2'b00;
     #10  $finish;
  end

The stuff in the Always block is RTL code. The stuff in the Initial block is not RTL Code. But both is Verilog Code.
 

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
The stuff in the Always block is RTL code. The stuff in the Initial block is not RTL Code. But both is Verilog Code.


Yes and yes. So yes. ;-)
 
  • Like
Reactions: digi001

    digi001

    Points: 2
    Helpful Answer Positive Rating

dave_59

Advanced Member level 3
Joined
Dec 15, 2011
Messages
816
Helped
361
Reputation
726
Reaction score
354
Trophy points
1,353
Location
Fremont, CA, USA
Activity points
6,613
RTL stands for Register transfer level. Basically code that describes the behaviour of a synthesisable circuit. This could be any language. So any code in any language that is synthesisable is RTL code.
I know I'm being a bit pedantic here, but not all synthesizable code is RTL. RTL is a coding style and level of abstraction that most synthesis tools support as their primary input. It describes logic in terms of data that moves from register-to-register on a clock cycle basis. There are higher and lower levels of coding abstraction that are also synthesizable, i.e. behavioral-level, and primitive-level.

You can also write RTL code that is not synthesizable, but generally the term has come to mean synthesizable RTL.
 

verylsi

Full Member level 2
Joined
Mar 12, 2012
Messages
123
Helped
16
Reputation
32
Reaction score
16
Trophy points
1,308
Activity points
2,130
Hey digi 001,

You were right about it, that the code in the "always" block is RTL code, that is because if you synthesize that , it can be synthesized and can be transformed into real circuit.
But the later part is a test bench - which is used to simulate the code.. its purpose is verification of an RTL and not to be synthesized. That is why it is not an RTL. again yes, it is a part of verilog only. so that testbenches can be written.

verylsi
 
  • Like
Reactions: digi001

    digi001

    Points: 2
    Helpful Answer Positive Rating

digi001

Full Member level 5
Joined
Apr 5, 2011
Messages
244
Helped
22
Reputation
44
Reaction score
21
Trophy points
1,298
Activity points
2,904
I know I'm being a bit pedantic here, but not all synthesizable code is RTL. RTL is a coding style and level of abstraction that most synthesis tools support as their primary input. It describes logic in terms of data that moves from register-to-register on a clock cycle basis. There are higher and lower levels of coding abstraction that are also synthesizable, i.e. behavioral-level, and primitive-level.

You can also write RTL code that is not synthesizable, but generally the term has come to mean synthesizable RTL.

Ok see this is where I get confused. Can you provide an example of this?
 

dave_59

Advanced Member level 3
Joined
Dec 15, 2011
Messages
816
Helped
361
Reputation
726
Reaction score
354
Trophy points
1,353
Location
Fremont, CA, USA
Activity points
6,613
Now I'm really going to get pedantic with the definition of the word synthesizable. Technically, any code you can simulate is synthesizable; it really depends on the capabilities of the synthesis tool and the technology you want to target. But here's a simple example:

Code:
reg [7:0] mem[10];
integer accum,sum,i;

initial 
        wait(!reset)
        forever @(posedge clk) begin
                   accum = 0;
                   for(i=0;i<10;i=i+1)
                          accum = accum + mem[i];
                   sum <= accum;
                  end

This is RTL because every clock cycle, the summation of the memory contents are transferred to register sum. It is not considered synthesizable because
  • most tools do not look at initial blocks
  • most tools do not synthesize wait statements
  • most technologies to not allow you to access more than one memory element in a single clock cycle.
But there are tools that could synthesize this into hardware.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top