u24c02
Advanced Member level 1
Hi.
I'm trying to implement formality with RTL and netlist which is scan and clock gating inserted netlist.
When I trying to check formal between RTL and netlist(not clock gating and not scan insertion) then they are no mismatch.
But when I insterted scan and clock gating, then they are not equality. But I'm not sure what am I supposed to do ?
I just use these commends as following,
set_clock_gating_style - blar~blar -control_signal scan_enable
compile_ultra -gate_clock -scan ~blar ~blar
I'm trying to implement formality with RTL and netlist which is scan and clock gating inserted netlist.
When I trying to check formal between RTL and netlist(not clock gating and not scan insertion) then they are no mismatch.
But when I insterted scan and clock gating, then they are not equality. But I'm not sure what am I supposed to do ?
I just use these commends as following,
set_clock_gating_style - blar~blar -control_signal scan_enable
compile_ultra -gate_clock -scan ~blar ~blar