RS-485 transceiver design

[xihuwang]

Hi , every one :
I am designing a rs-485 transceiver. I have some quesions :
1. The input common mode range of the reciever is -7 - +12V . I want to
know how to get this with +5V powr supply without generating
safty problem ( such as the Drain-buck pn junction forward conductinng) ?
2. The ESD should be 6kV . But the foundry ESD library cell just has
ESD structure (GGNMOS) with 2kV ability (BiCMOS or BCD process). What
should I do ?
3. Does anybody has RS-485 design experiece or docs ?
Thanks forward !

 

[dick_freebird]

RS-482 and RS-422 ESD is an interesting problem. The high
common moderange requires a resistor divider (though I
once had someone tell me they made a receiver that used
no resistor divider, they were unwilling to share details).
The ESD needs to not bind up the common mode input
range. That most likely means an isolated resistor which will
have to be sized for high thermal pulse input, with clamps
inboard of the front series resistor. You will want to understand
the pulsed power input of an ESD event, and the power-to-blow
capability of the resistors. You also need to maintain a good
enough lateral spacing in the resistors (anything that will
see the kV) to prevent spark-gap action, and not put the
resistor under power bussing, perhaps even make the input
pads "custom" (leaving out maybe the first couple of metal
layers at the bottom) to ensure there won't be a Met1-substrate
punchthrough (think 7MV/cm or so).

Standard ESD cells will not help you, they're going to dump
forward into vdd well below your upper CM limit and ground
well above the lower.