RS 232 uart xilinx macros -xapp223

[blackhawk155]

Hi,
I have problem with using uart macro from xilinx -xapp223 , I've tried to test the marco in activeHDL but it just keep giving me Uninitialized
serial out and buffer full and I don't know what is the problem ? do i have to download some library for activeHDL to use the macro or do any thing else to solve this problem ? !! plz help me if you know

here is my code to test the uart_tx ... i only generate the en_16_x_baud and use the .edn file as component
(note :code is only for simulating .. I'm not gonna implemented in hardware )

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity test is
port (din : in STD_LOGIC_VECTOR (7 downto 0);
write : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC;
buffer_full : out STD_LOGIC);
end test;

--}} End of automatically maintained section

architecture test of test is
signal clk_div: std_logic ; -- en_16_x_baud is clk_div
signal count_toDiv: integer range 0 to 7 ;
component uart_tx is
port ( din : in STD_LOGIC_VECTOR (7 downto 0);
write : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
en_16_x_baud : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC;
buffer_full : out STD_LOGIC);
end component;
begin
tx_comp: uart_tx port map(din,write,reset_buffer,clk_div,clk,serial_out,buffer_full);


process(clk,reset_buffer)
begin
if(reset_buffer='1')then
count_toDiv<=0;
clk_div<='0';
elsif(clk'event and clk='1')then
if(count_toDiv=7)then
clk_div<=not clk_div;
count_toDiv<=0;
else
count_toDiv<=count_toDiv+1;
end if;

end if;
end process;

end test;

 

[TrickyDicky]

If you're testing it - wheres the testbench? All this code is divide the incoming clock by 8

 

[blackhawk155]

the code divide the clock and then use the macro as component
here is my testbench code :


library ieee;
use ieee.std_logic_1164.all;

-- Add your library and packages declaration here ...

entity test_tb is
end test_tb;

architecture TB_ARCHITECTURE of test_tb is
-- Component declaration of the tested unit
component test
port(
din : in STD_LOGIC_VECTOR(7 downto 0);
write : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
clk : in STD_LOGIC;
serial_out : out STD_LOGIC;
buffer_full : out STD_LOGIC );
end component;

-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal din : STD_LOGIC_VECTOR(7 downto 0);
signal write : STD_LOGIC;
signal reset_buffer : STD_LOGIC;
signal clk : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal serial_out : STD_LOGIC;
signal buffer_full : STD_LOGIC;

-- Add your code here ...

begin

-- Unit Under Test port map
UUT : test
port map (
din => din,
write => write,
reset_buffer => reset_buffer,
clk => clk,
serial_out => serial_out,
buffer_full => buffer_full
);

-- Add your stimulus here ...
process
begin
clk <= '1' ;
wait for 10 ns ;
clk<= '0' ;
wait for 10 ns ;
end process ;

tbrocess
begin
reset_buffer<='0','1'after 5ns,'0'after 90ns;
din<="00000000", "10101010" after 90ns;
write<='0','1'after 1000 ns,'0' after 2000 ns;

wait;
end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_test of test_tb is
for TB_ARCHITECTURE
for UUT : test
use entity work.test(test);
end for;
end for;
end TESTBENCH_FOR_test;

 

[blackhawk155]

please if any one knows what wrong with my code please tell ? ! :roll:

 

[TrickyDicky]

what is it thats uninitialised? can you paost a waveform?

 

[blackhawk155]

as you can see that the serial out and the buffer_full is uninitialized and i don't know what is the problem

 

[TrickyDicky]

looking at the waveform, you never set the write signal high.

 

[blackhawk155]

this another zoomed shot
as you can see i set the write signal but the serial_out and the buffer_ful still uninitailized

 

[TrickyDicky]

I guess this is one for you to debug. I have no idea whats wrong without the code for uart_tx. This is what us engineers do.

 

[blackhawk155]

If i know the code of the uart_tx i would debug it but thanks any way :smile: