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RS-232 Receiver and Transmitter Design in VHDL

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ikki

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rs232 vhdl

hi there, Im just wondering where I can get the VHDL code for Rs-232 receiver and transmitter design ? ...

Im planning to use this code to implement on Xilinx spartan 3 FPGA..

Added after 59 seconds:

pls send file to my email at jasperng10@gmail.com thanks
 

FvM

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vhdl rs232

I remember several forum posts in the last six months, some with example code or links. Also opencores.org has more than one UART project.
 

ikki

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vhdl rs232 uart

thanks for your reply,

i searched opencores.org ... however i dont see rs232 UART project there. Actually there is one but it is not the one im finding...

for this forum i searched thru too, ... but i didnt find anything matches my likings

>.<
 

ikki

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rs232 receiver vhdl

Erm, just wondering does anyone have the architecture/ block diagram of a RS232 bus controller ? ..
 

FvM

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rs232 vhdl code

Another, more basic UART project from

but i didnt find anything matches my likings
You may rather like to design your own UART, it isn't that difficult and instructive anyway.
 

ikki

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vhdl rs232 code

Thanks for the link ...

Im just wondering how do i come out with the state machine for transmission part of the RS232 UART ? ...

any guide to follow ? ..
 

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rs232 vhd

Transmission is most easy, cause it don't need oversampling. Just count 10 bit times with your baud clock. Assuming, your TX bit counter has an idle state of zero. it would emit the start bit at 1, 8 data bits on 2 to 9 and a stop bit at 10, then fall back to idle.
 

ikki

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vhdl for rs232

do i set a signal with witdth of 9 downto 0 ? or should i use 8 downto 0 and send '1' to Txd line when the count reaches 9 ? ..
 

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vhdl rs232 transmitter

There are some basic principles.

First thing you can do is study the operation of a UART of any 8 bit microcontroller, and you will know the registers, signals, control involved.

In that kind of receiver-transmitter, the receiver is more complex than the transmitter.

The transmitter consists only of a state machine of N states depending on the number of bits of the serial transmission. The bit generated on each state depends on the bits stored in the TX register.

In the receiver side it has to detect the start bit, and then pick up the transmited data bits, usually they do this by sampling data at a frequency higher than the UART transmission rate, once it detecs the start bit you synchronize the state machine with UART clock and pick up the data bits, then store them in the RX register.

Basically that´s what you have to do.
Salutes
 

jleslie48

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vhdl rs232 receiver

Quote:" Another, more basic UART project from

Quote:
but i didnt find anything matches my likings
You may rather like to design your own UART, it isn't that difficult and instructive anyway."


Hello all,

I just surfed in looking for a VHDL tutuorial demonstrating RS232 communications.

I'm just starting with VHDL and have the Digilent Virtex-II development system with the ISE 10.1 and Impact 10.1 software packages:

https://www.xilinx.com/products/devkits/XUPV2P.htm

To date, with help I've only managed to write a simple program to respond to some of the switches and digital inputs to control the on-board digital led's. I'm an experienced C programmer, and have even done some PLC programming, but this environment is very foreign to me.

I would love to reverse engineer the example from above, but I'm too green to know how to hook up all those vhd files with my ucf files, and fire this thing up. Does anybody have a walk-through of this example loaded up, locked and loaded that I can follow?

And since I want the world, I'm going to have to expand this example to some data processing. Now in C I'd throw all the ascii characters in a nice string array, and then do some strstr functions looking for my command strings, and then send some nice ascii strings out another UART and an ACK back to the source UART, but I'm not even sure how the idea of strstr and character buffers works in this VHDL world.

Ok, santa that's about it, any help out there?

TIA,

Jonathan
 

kyawsoelwin

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rs232 in vhdl+pdf

Read On this

Inside this Not Only Complete UART RxTx, RS232 RxTx Core in VHDL soruce codes but also step by step explaination are included.
You can develop as your desine as well.

Enjoy it.
 

jleslie48

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rs 232 vhdl

kyawsoelwin said:
Read On this

Inside this Not Only Complete UART RxTx, RS232 RxTx Core in VHDL soruce codes but also step by step explaination are included.
You can develop as your desine as well.

Enjoy it.

OH THANK YOU!!!! I just downloaded it I can't wait to try it out. I'll give a full report shortly.
 

jleslie48

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rs-232 vhdl+fpga

kyawsoelwin said:
Read On this

Inside this Not Only Complete UART RxTx, RS232 RxTx Core in VHDL soruce codes but also step by step explaination are included.
You can develop as your desine as well.

Enjoy it.


Ok, I'm going through this chapter. Its very well written, and I've even gone ahead and ordered the book its from. Quick question.

the article introduces on book in section 7.2.4 A flag FF. What is a Flag FF? does the FF stand for flip flop? I can't find a definition.


Sincerely,

Jon
 

kyawsoelwin

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vhdl rs 232

Ok, I'm going through this chapter. Its very well written, and I've even gone ahead and ordered the book its from. Quick question.

the article introduces on book in section 7.2.4 A flag FF. What is a Flag FF? does the FF stand for flip flop? I can't find a definition.


Sincerely,

Jon


Oh Sorry! some files are missing in that file. it refers to the previous chapters.
okie!!
download all chapters here.!!!

https://ifile.it/hl5s1iy

In this chapter FF means Flag pointer for First in Fast Out Buffer.

okie
enjoy it.
 

jleslie48

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vhdl uart receiver

kyawsoelwin said:
Ok, I'm going through this chapter. Its very well written, and I've even gone ahead and ordered the book its from. Quick question.

the article introduces on book in section 7.2.4 A flag FF. What is a Flag FF? does the FF stand for flip flop? I can't find a definition.


Sincerely,

Jon


Oh Sorry! some files are missing in that file. it refers to the previous chapters.
okie!!
download all chapters here.!!!

https://ifile.it/hl5s1iy

In this chapter FF means Flag pointer for First in Fast Out Buffer.

okie
enjoy it.

LOL!!! I just picked up a copy of the whole book, hard copy and even the pdf for searching. It's a great book. I'm going through it now (I'm scared to lock and load, and just run the RS232 example.) This is great stuff. Its all clicking now, this is exactly what I wanted, I just read up on the circular FIFO buffer, love it.

In the example they haven't mentioned the .UCF file, I just started with chapter 1, but I imagine that I have to resolve RX and TX to the pinouts of my evaluation board. I'll be posting my progress (more likely questions) as I go.
 

jleslie48

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verilog code for rs232

Here's my version of a blog on how to get this UART working. Its a complete backup of my workspace
on the project in its natural tree form, and there is also a zip file of the project if you want to download it in
one fail swoop (3mb) the backup is here:
https://jleslie48.com/fpga_uartjl_01/

and the zip file of that is here:
https://jleslie48.com/fpga_uartjl_01/zip090120a_fpga_uartjl_01.zip

You will also notice a notes sub-directory where these notes and discoveries are being
documented here:
https://jleslie48.com/fpga_uartjl_01/notes/

I even used microsoft word to try and clean up the notes.txt file a bit.

Anyway, here is the project so far, and I'd appreciate some insight as detailed in step 6) below.

- Jon



Notes.txt:

090120

- ok so I started this project and I admit it, I'm scared and I don't really know what I'm doing.

I have the Digilent Virtex-II development system with the ISE 10.1 and Impact 10.1 software packages:

https://www.xilinx.com/products/devkits/XUPV2P.htm



This project started with the sources and chapter 7 of:

FPGA PROTOTYPING
BY VHDL EXAMPLES
Xilinx SpartanTM-3V ersion
Pong P. Chu
Cleveland State University

the authors website has even a download of the examples:

https://academic.csuohio.edu/chu_p/rtl/fpga_vhdl.html

and even chapter 7 as a pdf file:

https://academic.csuohio.edu/chu_p/rtl/fpga_vhdl_book/fpga_vhdl_sample_chapter.pdf

In this backup of my project,
all the examples from the book are stored in this tree as \vhdl_examples

and all the sources I think I need are stored in \orig because
I'm sure I'll be modifying them and so I wanted to store off my originals.
as I make milestones, I imagine new directories of backups will emerge,
named \buxx_somethingdescriptive

as this forray will also be kept online, I will zip it up and store it in the root
directory under zipYYMMDDx_somethingdescriptive.zip

so anyone wishing to follow in my footsteps or play along can do so.

with that said lets begin.

1) I started a new project with ISE 10.1 Project Navigator.

2) after that huba-balloo, I clicked 'add existing source' and added all the
source I thought I needed from the examples. I had previously put copies of
those sources in the root of the project.

I even took a screencap:
\notes\screencap01_firstsource.png
screencap01_firstsource.png



so far so good.

3) I then clicked 'synthesize -XST'. The arrows chasing each other thingy changed after
a few seconds to a spinny type thingy and the bottom view section started spewing
all kinds of report stuff. All well and good and I ended up with some warnings, which
I'd like to discuss a little later. Here's the screen cap:

\notes\screencap02_firstsynth.png
screencap02_firstsynth.png


the error messages are:

Analyzing Entity <uart_test> in library <work> (Architecture <arch>).
WARNING:Xst:753 - "C:/jon/fpga_uartjl_01/uart_test.vhd" line 29: Unconnected output port 'db_level' of component 'debounce'.
Entity <uart_test> analyzed. Unit <uart_test> generated.

Analyzing generic Entity <uart> in library <work> (Architecture <str_arch>).
DBIT = 8
DVSR = 163
DVSR_BIT = 8
FIFO_W = 2
SB_TICK = 16
WARNING:Xst:753 - "C:/jon/fpga_uartjl_01/uart_core.vhd" line 37: Unconnected output port 'q' of component 'mod_m_counter'.
WARNING:Xst:753 - "C:/jon/fpga_uartjl_01/uart_core.vhd" line 46: Unconnected output port 'full' of component 'fifo'.
Entity <uart> analyzed. Unit <uart> generated.

Now I haven't used a UCF file yet, and I believe that I must, so I'd like to discuss that in a very short time period,
but let's continue with what I have done so far.

4) I then hit the 'implement design' arrow thingy. It was very obedient and started spinning as well. whe it was all
done it was very happy. No errors or warnings. Here's the screen cap of that result:

\notes\screencap03_firstimplement.png
screencap03_firstimplement.png


5) checking the pinouts. well somewhere in my travels, someone mentioned looking at the pinout report for useful stuff.
so here it is:

\notes\screencap04_firstpinoutrpt.png
screencap04_firstpinoutrpt.png


6) well now I want to take a break and review a few things, I can see that my pinout report has some useful stuff and some
not-so useful stuff. for instance, RX and TX I think have to somehow be associated to the DB9 that is on my board (the
root directory has a UCF file RS232.UCF in it, that I believe I should use, and the pinouts of this "hard" uart should be
properly level shifted yes?) This example also assumed a spartan 3 evaluation kit which I guess has a digital readout
and I think that is what those led<x> things are, so I want to get rid of those. I also have a question about the clock
situation. the chapter describes that all the communication is to be synched up with a clock pulse divided by 16 * something
or other (see 7.2.2) now this is all well and good, but I imagine my system clock is different (ok, I admit it, I don't even
know where it is.) and so those calculations need to be adjusted.

So at this point I'm looking for advice and review of my work so far. Can anybody give some insight into the issues I've
raised in 6) above?
 

jleslie48

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vhdl rs232 link module

here is the latest of my build:

ERROR:ConstraintSystem:59 - Constraint <NET "RS232_DSR_OUT" LOC =
"AD10";>
ERROR:ConstraintSystem:59 - Constraint <NET "RS232_CTS_OUT" LOC =
"AE8";>
ERROR:ConstraintSystem:59 - Constraint <NET "RS232_RTS_IN" LOC =
"AK8";>
ERROR:ConstraintSystem:59 - Constraint <NET "RS232_DSR_OUT" IOSTANDARD
=
ERROR:ConstraintSystem:59 - Constraint <NET "RS232_CTS_OUT" IOSTANDARD
=
ERROR:ConstraintSystem:59 - Constraint <NET "RS232_RTS_IN" IOSTANDARD
=
ERROR:ConstraintSystem:59 - Constraint <NET "RS232_DSR_OUT" DRIVE =
8;>
ERROR:ConstraintSystem:59 - Constraint <NET "RS232_CTS_OUT" DRIVE =
8;>
ERROR:ConstraintSystem:59 - Constraint <NET "RS232_DSR_OUT" SLEW =
SLOW;>
ERROR:ConstraintSystem:59 - Constraint <NET "RS232_CTS_OUT" SLEW =
SLOW;>

\notes\screen05_firstucferrors.png

I don't know why it's just not ignoring the unused signals and now I
realized that the UCF file
uses the # as a comment out character instead of the the "--"
grrrrrrr.....

yup that's it.
\notes\screen06_ucffixed.png
\notes\screen07_pinoutrpt.png

Ok, this looks like a I successfully completed 'implement design'

added clocks.ucf to move clock to AJ15. all implimented still here's
clocks.ucf:

NET "clk" LOC = "AJ15";
NET "clk" IOSTANDARD = LVCMOS25;
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10.00 ns HIGH 50 %;

whatever this means.

now for the button,reset, and leds:

btn_db_unit: entity work.debounce(fsmd_arch)
port map(clk=>clk, reset=>reset, sw=>btn(0),
db_level=>open, db_tick=>btn_tick);
-- incremented data loop back
rec_data1 <= std_logic_vector(unsigned(rec_data)+1);
-- led display
led <= rec_data;
an <= "1110";
sseg <= '1' & (not tx_full) & "11" & (not rx_empty) & "111";

these are all S3 Board specific yes?
btn(0) is one of the 4 buttons of the S3 board and I have to
find mutatis mutandis on my Digilent board?
led(0-7) an(0-3) and sseg(0-7) are what exactly?

for functionality I think I only need btn(0) yes?

then comes the clk, where is the speed and the divisor value fit in?
- I'm guessing its somewhere in those oodles of pdf's that came with
te
board, I remember ug069.pdf being useful...

and for this project reset is just a placeholder yes?
 

SweetMusic

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vhdl rs2323 receiver

There is a version of that, or comething like that in verilog too ?
 

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