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ROM layout design using cadence

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rnkmukhrji

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Hii
I am a final year B.Tech student. As part of our final year project we have to design a ROM .. We have created our schematic and also extracted the basic layout from the schematic in Cadence.

Now, we have to make the connections and the wirings and also give proper design rules..


We are New to cadence and Layout design and are doing everything on our own


Needless to say, we feel like we are groping in the dark..... without a proper idea of how to achieve our target...
can anyone please help ??
 

Hii
I am a final year B.Tech student. As part of our final year project we have to design a ROM .. We have created our schematic and also extracted the basic layout from the schematic in Cadence.

Now, we have to make the connections and the wirings and also give proper design rules..


We are New to cadence and Layout design and are doing everything on our own


Needless to say, we feel like we are groping in the dark..... without a proper idea of how to achieve our target...
can anyone please help ??

Hi rnkmukhrji,

I am trying on the same thing. Did You get something.
 

First of all you have to decide which technology you will use e.g 22nm, 14nm or something else (these are the current technology). And when we talk about technology, say for example 22nm technology we mean that the smallest gate length is 22nm. Then you have to find out the foundry-book where all the DRC and other rules are written. These are provided by the Fabrication Lab. I haven't yet seen anything like that, but there must be one, I heard of it. Or else how the DRC run checks?
Then you need some tutorial to familiar with the tool.
 

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  • Cadence Cell Design tutotial.pdf
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