Rom inference in Verilog

[amolgupta87]

I have a logic function to implement. It's quite an odd/irregular one and large. I have a truth table to represent it. In order to implement it i would like to have a constant array having. How can I have an array in verilog which also gets synthesized(what construct / keyword). The value of array will not change.

P.S. my synthesis tool is rc from cadence.

 

[shanmugaveld]

Am not sure try this
Declare 2d array

assign a[0] = 5'd1;
assign a[1] = 5'd2;

since we are driving the constant, i felt that tool may infer this as ROM.