ROM in verilog and recalling it in a module

[Mina Magdy]

can i recall a rom more than one time (360 time) in the same clock in the verilog
i mean will the synthesis tool regard it as a Rom ar as a Registes
the rom i made is 500000*1 was that ok or no?

 

[FvM]

I presume you want to infer a ROM from behavioral Verilog code. Depending on the FPGA hardware, it's a single- or dual-port block memory. This means, you can't access more than two different addresses at the same time (in one clock cyle).

You'll also have checked the available internal memory capacity of your FPGA.