rom from matlab to vhdl to be synthesised

[Bustigo]

i have a rom like this generated from matlab
01010111111111111111
01010000000000111111
01010111111110011111
---
----
01010111111011111111
01010111001111111111

manually i copy this vectors to vhdl and put them betwwen "" in a constatnt array
now, the problem that this rom become bigger i would like to do that with an easy method
:!:

 

[TrickyDicky]

What is the ROM? is it the output of a specific function? could you not implement the function in VHDL to initialise a ROM?

for example, you could generate a SIN table like this in VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;

library floatfixlib;
use floatfixlib.fixed_pkg.all;


.....

type sin_table_t is array(0 to 255) of sfixed(1 downto -6);
function make_sin_table return sin_table is
  variable ret : sin_table_t;
begin
  
  for i in ret'range loop
    ret(i) := to_sfixed( SIN( (MATH_PI*i)/256) ), ret(i));
  end loop;
  
  return ret;  
end function;

Constant SIN_TABLE : sin_table_t := make_sin_table;

If you're using Xilinx, you can use textio in a function (like above) to read a text file into an array. (altera wont let you do this - open a mysupport case and request it!)
Or use TCL to generate the constant for you in a VHDL package.