Ring oscillator question

[AMSA84]

Hello guys,

I'd like to know if someone here has experience on ring-oscillators. My questions is to know if the generated frequency from ring oscillator varies too much with the supply voltage?

 

[dick_freebird]

A CMOS inverter ring will vary a lot with Vdd. About the same
ratio as your IDsat (since capacitance changes not much).

A bare ring oscillator can be tough to test especially at probe,
the edges against bondwire or probe inductance can make the
ring unstable (kill oscillation, etc.). Well designed ROs may have
a high #bit counter appended to help this.

 

[AMSA84]

So what is the way that one can have a stable rectangular waveform?

 

[AMSA84]

What I meant was which kind of circuit can be implemented to obtain a nice rectangular waveform and stable frequency?

 

[Vbase]

At what frequency and what voltage you need nice square waveform?

 

[dick_freebird]

For a near constant frequency I would recommend a ring
with large per-stage non-junction, non-MOS capacitors
(as these will vary with temp and voltage as well) and a
current starved inverter (i.e. current controlled). Then
your transition is all about I=CdV/dt and I, C are fixed
(to the quality of your current reference).

Now if you had a low-TCR resistor and low-TCC capacitor
and were operating at a low-ish frequency (few MHz or
lower) I might recommend a switched-RC single stage
oscillator with VDD/3 and 2*VDD/3 threshold comparators.
Now you will not have a true triangle, but close, and you
will have charge / discharge current which is proportional
to VDD but so are your reference levels; the only varying
parts are the comparator delays (hence the freq limit).
I have had decent results using this style in PWM designs.
Never perfect, but within spec windows for fosc that such
products tend to demand. And no reference accuracy to
achieve.

This scheme is what the venerable LM555 used, and for
pretty good reasons.

 

[AMSA84]

Hi freebird and thank you for your suggestions. However, allow me to ask you what you mean by a ring with large per-stage non-junction?

Do you have any reference on this? Paper, white paper, book? BTW, the desired frequency is > 300MHz, so I should go the first option that you have recommended.

- - - Updated - - -

EDIT: freebird, I found this: http://edg.uchicago.edu/projects/sampling_chip/counter_oscillator.pdf This is what you were referring to?

 

[dick_freebird]

What I meant was, you would like the timing element (C)
to not be a junction cap (C-V and temperature variability)
or MOS cap (C-V, and maybe a little tempco). A simple
ring oscillator often is only self-loaded stages and that
loading (C) is mostly junction, D-B. Not to mention that
the charging current is way variable in itself.

You'd like the majority of the timing capacitance to be
invariant (or else, make the timing current cancel that
variability, which would be more of an exercise). So, a
large-ish (if you are not up against technology speed)
invariant capacitor removes one source of supply (and
make, and temp) variation (or at least sandbags the
variation-contribution of the actives).

I can't see the details of voltage controlled delay stage
in that presentation, to say whether it is or isn't like
what I describe. I believe all of the documentation of
my designs remains the property of a former employer.

 

[kartheekRP]

ring oscillator in cadence:
increased stages from 9 to 17 for minimum w/l ratio and intermediate outputs of ring oscillator fed to driver chain (starting with same w/l as R.O. inverter),wanted frequency increment but frequency is decreasing,why?And how to increase frequency of ring oscillator?