# Ring Oscillator - looking for good examples

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#### odyseus Ring Oscillator

Hi all,

I'm trying to match the theory with a simulation of a three stage ring oscillator using CMOS inverters (ie a P & N device with the gates connected together on the input and the drains connected together on the output).

The theory says you match the W/L ratios (because Kp & Kn are different) to get a symetrical waveform - so far so good.

The oscillating frequency is root 3 times the R-C of a single stage.

The R is equal to 1/(IDS(lambdaN+lamdaP) where IDS is calculated assuming that VDD/2 is applied to each gate.

With my example WP=2um, WN,LN,LP = 1um; Kp = 110E-6 & Kn = 50E-6
VDD=5V, VT = 0.7V

and gives R as ~ 37K so with a 1pF connected as the load the oscillator should work at ~7MHz but ADS simulation shows it working at 40MHz !!

This equates to R being equal to about 4K

Any ideas or any good worked examples ??? :?

#### flatulent Re: Ring Oscillator

I suspect that @ds thinks that it is an analog circuit and finds the frequency at where the phase shift is 60 degrees per stage. (180 extra around the loop) so the square root function does not hold.

This still does not make your frequency come out right, but still may be one of the sources of error.

#### BigBoss Re: Ring Oscillator

I don't know the phenomena in this case but transient analysis may give better result. In fact oscillator frequency prediction feature of ADS does not work in all case. For instance in my symmetrical 5.8GHz RFCMOS oscillator circuit HB didn't converge. To get it right plane , I have applied a few 1G Ohm resistors some "floating" points. ADS doesn't love floating connections. :!:

Namely , before Oscillator analysis, a transient analysis can be done and could it be inserted in option box as a initial state.. :roll:

Regards

#### odyseus Re: Ring Oscillator

I tried using resistive loads and a simple C-S stage for each cell, and DC decoupled to allow AC analysis. The break points came out in the correct place with the right phase.

The inverter circuit was analysed using a transient simulator ie Pspice, with an initial condition set on the feedback loop to allow simulation.

I suspect my assumptions of the inverter are incorrect..

Under normal conditions one device will be off and the other on - no current will flow ie when the input is VDD or 0V. As the voltage changes both devices will turn on and the most current will flow at VDD/2 on the gates. This current I have used to calculate the output resistance, but as I said there is something fundamentally wrong ???

#### BigBoss Re: Ring Oscillator

You have to assign a initial conditions for some "floating point" . In Cadence it's very easy but I don't know which simulator do you use..

Main outout of a inverter is a "floating point". Simulator can not decide that this node is initially 0 or Vdd and may start a wrong points then continues.

#### odyseus Re: Ring Oscillator

This is odd,

I have now analysed the ring oscillator using ADS Harmonic balance and it too oscillates at 40MHz with a phase noise of -105dBc/Hz at 10Khz offset. This agrees with the time-domain (Transient) simulation.

If I perform an AC analysis and bias each stage with 2.5V on the gates but isolate each stage from the other using an ideal DC block, the ac analysis shows the 0 degree point to agree with my theory in that oscillation should occur at 4MHz.

Have I calculated Rload correctly ie calculate IDS with 2.5V applied then use the equation Rload = 1/(IDS(LamdaP+LamdaN)) ???

I just can't understand the descrepency ????

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