Ring Oscillator Design VHDL

Status
Not open for further replies.
S

Shahin Bayat

Newbie level 4
Joined
May 20, 2015
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
37
Hey guys,

I need to implement some ring oscillators in Vivado on my Nexys4 FPGA from Xilinx and was wondering if anyone has some source code VHDL for a ring oscillator?

I haven't used VHDL in a very long time and can benefit from such source code. I understand that I need to have an odd number of inverters chained together. I finally need to connect the output signal of the very last inverter to one of the general purpose IOs and measure with an oscilloscope?

Please correct me if I'm wrong.

Also, my assumption is that you need a way of setting some constraints on the loop or you would get some errors?

Thanks! :bang:
 

Without constraints that directs the synthesis tool to keep redundant logic cells, or using low level primitives to describe the circuit, you won't get a working ring oscillator.

I could tell you how to do it in Altera Quartus, I'm not using Xilinx. But I'm quite sure that it's possible with Xilinx tools, most likely you'll find respective hints in Xilinx forums.
 




This sounds way too complicated...

I have written the VHDL code for the following image and the code is attached:


Is it possible to synthesize this and attach an oscilloscope to the output of the oscillator or just read the output of the counter? I'm new to FPGAs, so your reply makes no sense to me...

Thanks,
 

Attachments

  • source.zip
    3.8 KB · Views: 102

Without the "complicated" lut primitives, the syntheses tool will simply minimise the not gate chain into a single not gate or just a wire (depending on how many not gates).

Also, each compilation would get you a different result, as it places the logic randomly in the FPGA each time.
 

I'm not sure if you actually read what has been written above about removal of redundant logic cells. Your "ring oscillator" is likely to be reduced to a single inverter during synthesis. But it's quite easy to compile the design and review the gate level output. So just try.

The other point is that you shouldn't expect any meaningful output from your counter construct because it misses to synchronize the signals from unrelated clock domains.
 



Well, do you have a link to a tutorial on how to design such a circuit using LUT premitives? I'm using the Nexys 4 board from Digilent... I've never done anything like this at all, just very basic FPGA designs.
 


Sorry I didn't understand your initial post at all. It's starting to make more sense now though. It would be very nice if you could provide a link to a guide to how to implement such structures. I'm using Nexys 4 from Digilent and also the Vivado 2015 design suit..

Thanks!
 


Seriously it's too complicated to instantiate a bunch of LUTs configured as inverters? I could write this in like 10 lines of code in Verilog including the module declaration stuff. Probably take 20 lines in VHDL.

Here is the Verilog version:
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10

module ro #(parameter N = 9) (output o, input e);
  wire [N:0] ro_sig;
  generate genvar i;
    for (i=0;i<N;i=i+1) begin : gen_luts
      LUT1 # (.INIT(2'b01)) inst (.O(ro_sig[i+1]), .I0(ro_sig[i]));
    end
    assign ro_sig[0] = ro_sig[N] & e;
    assign o = ro_sig[N];
  endgenerate
endmodule

where
I0 O
0 INIT[0]
1 INIT[1]

Optimizations could include using LUT1_L for local CLB routing and only using the LUT1s when N causes the implementation to spill over into another CLB.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…