Ring counter implementation in vhdl

[poornimayn]

Hi,
I'm a newbie in VHDL. I'm trying to implement 4 bit Ring counter using DFF.
I'm using one preset DFF and other FF has a reset for initialzing purpose.
I could able to preset/reset the value but not able to shift the value in the Flip flop ring after reset/Preset.
I'm using Xlinx ISE 14.3 . I'm facing problem while simulating the counter!!..

Below is the code for Preset DFF and Reset DFF and also for Ring counter.

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Code VHDL - [expand]
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----PRESET DFF-------
 
entity DFFPreset is
    Port ( preset : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           d : in  STD_LOGIC;
           q : out  STD_LOGIC);
end DFFPreset;
 
architecture Behavioral of DFFPreset is
 
begin
 
process(clk,preset)
begin
if preset ='1' then
q<='1';
elsif clk'event and clk ='1' then
q<=d;
end if;
 
end process;
 
end Behavioral;
 
 
 
 
---------RESET DFF---------
 
 
entity DFF is
    Port ( reset : in STD_LOGIC;
            clk : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end DFF;
 
architecture Behavioral of DFF is
 
begin
process(clk,reset)
begin
 
if reset='1' then
Q <= '0';    -- clear register
elsif (clk'event and clk='1') then
Q<=D; --positive edge of clock is used
end if;
 
end process;
 
end Behavioral;
 
 
 
-------------------4 bit Ring COunter-----------------
 
entity ringcounter is
    Port ( reset : in STD_LOGIC;
            clk : in  STD_LOGIC;
              preset : in STD_LOGIC;
           count : out  STD_LOGIC_VECTOR (3 downto 0));
end ringcounter;
 
architecture Behavioral of ringcounter is
 
signal q0,q1,q2 : STD_LOGIC := '0'; ---initialising the signals
--signal temp :STD_LOGIC := '1'; --not using it as of now.
signal q3 :STD_LOGIC := '1';
 
component DFF is
    Port ( reset : in STD_LOGIC;
            clk : in  STD_LOGIC;
            D : in  STD_LOGIC;
            Q : out  STD_LOGIC);
end component;
 
component DFFPreset is
    Port ( preset : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           d : in  STD_LOGIC;
           q : out  STD_LOGIC);
end component;
 
 
begin
 
 
DFFPreset1 : DFFPreset port map(preset,clk,q3,q0);
DFF2         : DFF port map(reset,clk,q0,q1);
DFF3         : DFF port map(reset,clk,q1,q2);
DFF4         : DFF port map(reset,clk,q2,q3);
 
count <= q3&q2&q1&q0;
 
end Behavioral;

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[rahul.achates]

you need to add below lines , since this is one file and you have used 3 entity , you need to declare both lines 3 times , just before the entity .... once you done ..your code is good to go ..

library ieee;
use ieee.std_logic_1164.all;


Rahul

- - - Updated - - -

Let me know if you encounter any other issue

 

[poornimayn]

I have added the lines you have mentioned in my code. The DFF files are in different files in the same workspace, I have just instantiated then by declaring component of DFF.

 

[rahul.achates]

Your issue resolved ??

Rahul

 

[poornimayn]

I guess I have to make it further clear to make you understand my problem.

simulate the code using simulator and
Step 1> Force reset/preset values of the flip flop.
Step 2>In addition to the above step I force the clock also.
Step3>Now I click on run I could see the initialised values on the Flip flop output.


Now My intention is to circulate these set values in the RingCounter.

How do I do it?

Does it require modification in the code?
Or Am I going wrong in the way I force the input and make the observation?