Your current density rule is predicated on some maximum temp,
service factor and lifetime required. For me, that's 125C, 100%,
10 years. Somebody making a singing Christmas card chip might
be a little less demanding.
With such short fingers and already violating current density,
you may want to look more closely at power density and self
heating as well.
You could consider taking the current out vertically (vias to
a Met2 or higher comb) so that Met1 width is not the constraint.
You can have a high fill factor at higher levels and you can do
taper structures and space FET cells apart without capacitance
penalty in higher-power structures. Using your top, thick metal
layer would be a good idea for a power amp (as well as minimizing
substrate capacitance, at the cost of all those vias' resistance).
Given that power density is a likely issue, you might elect to not
make the FET a minimum-minimum-minimum device but use
(say) a 2xN source and drain region shared, getting at least 2X
the metal width. Yes, this adds S/D bottom plate area.