Reverting from a std_logic_vector(0 to n) to std_logic_vector(n downto 0)

[mmp131316]

Hello everybody:wink:,
i want to ask if anybody knows how to invert the bits order from a std_logic
-vector from a 0 to n to -> n downto 0
For example i am having the signal s : std_logic_vector(0 to 3) := "1010" and i want it to be 0101
3 downto 0?
Is there some kind of function??

Thanks for youre time:wink:

 

[SPIZERO]

function invert (S : std_logic_vector(0 to N)) return std_logic_vector(N downto 0) is
variable Y : std_logic_vector(N downto 0);
begin
for i in 0 to N loop
Y(i) <= S(i);
end loop;
return Y;
end function;

try it! there might be an error. I hope that you can solve them.
N must be a constant in one case.

 

[mmp131316]

thanks for the tip:wink: however i was looking for a sort of built in function or something with which i could do this inversion in one shot

 

[TrickyDicky]

SPIZ, that is not a very generic function. it would be far better to use attributes.

function invert (S : std_logic_vector) return std_logic_vector is
  variable Y : std_logic_vector(s'range);
begin
  for i in s'range loop
    Y(i) <= S(S'high-i);
  end loop;

  return Y;
end function;

This way it will flip a bus round that is decalred as to or downto of any size.

But the origional poster asked for a (0 to n) conversion to a (n downto 0) conversion. if you really wanted that, you can just assign a (0 to n) to a (n downto 0) signal:

signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(0 to 3);

...

a <= "1010";
b <= a;

While the bit order is the same, and will displayed the same in modelsim, the bits will be assigned like:

a(0) => b(3)
a(1) => b(2)
a(2) => b(1)
a(3) => b(0)