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Results for hierarchical LVS

aditya1579

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Hi,

Suppose I have an incorrect nets error at the cell level in lvs.

For eg: if I have a cell and2x2, and the tool is reporting "incorrect nets" error under this cell, besides the top level cell.

My question is, since there are many occurrences of the above cell in the layout and source, on what basis is this "incorrect nets" error reported ?

Because it may so happen that one instance of the and2x2 cell is properly connected, but some other instances are not.

In other words, can someone please explain to me how the reporting for lvs is done hierarchically ?

Thanks.
 

Prashanthanilm

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In General,
Suppose you give AND cell as hier cell.
If the cell itself is failing, then it means the netlist and gds2 of Cell is not proper.
If the Failure is a top, you need to track the netlist/spice from the error report.
 

CambridgeLv

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No matter the subckts in your spice or cdl file whatever, or the cells in your gds, the same cell, subckt only exist once, they will be instantiated one or more times to build your top design. Then the tool check each circuit unit only one time.
 

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