Resonant Swtiched Capacitor with Arduino

[jangmel]

Hello! Good day.

I plan to make a 3 Cell Active Balancing circuit using Arduino Uno.
It uses the Resonant swtiched capacitor method.
The MOSFETs(IRFZ40N) 1, 3, 5 and MOSFETs 2, 4, and 6 are given PWMs of opposite phases.
However, sometimes this causes certain cells to discharge rapidly.

I use a PWM of 2.33 kHz. One cycle of 2.33 kHz is 429us, and has a dead time of 10-20us.

First of all, what I'm most curious about is

1. Where should I connect Arduino's GND.
I'm currently connecting Arduino's gnd to the sources of MOSFETs 3, 4, 5, and 6.
I wonder if this is wrong. If it is wrong, I wonder which part I should connect Arduino gnd.

2. I wonder if I can connect Arduino's GND with the (-) of the power supply I use for the gate driver (TC4427).
If this is the wrong way, does the VDD and GND of TC4427 just need to connect to (+) and (-) of the power supply, and Arduino's GND only need to connect to the source of the MOSFET?

Sorry for the long question. I need the help of wise people.
Thank you! Have a nice day.

 

[FvM]

I'm currently connecting Arduino's gnd to the sources of MOSFETs 3, 4, 5, and 6.

How? All four nodes have different potential.

Unfortunately there's no simple way to implement gate driver for three stacked half-bridges. You should start with fixing the requirements:
1. each MOSFET must be driven with Vgs <= 0 V in off-state
2. each MOSFET must be driven with Vgs > Vgs,on, e.g. 6 or 8V in on-state
3. Vgs maximum rating of +/- 20 V must be never exceeded for any MOSFET
4. TC4427 GND must be tied to logic ground

To fulfill 1. TC4427 GND could be tied Q6 source (most negative battery voltage). With driver supply of 18V and battery charging voltage limited to e.g. 4.2 V per cell, the circuit can marginally work (fulfilling 2. and 3.). You can visualize individual Vgs values in a simulation. But it's a real bad design.

 

[jangmel]

How? All four nodes have different potential.

Unfortunately there's no simple way to implement gate driver for three stacked half-bridges. You should start with fixing the requirements:
1. each MOSFET must be driven with Vgs <= 0 V in off-state
2. each MOSFET must be driven with Vgs > Vgs,on, e.g. 6 or 8V in on-state
3. Vgs maximum rating of +/- 20 V must be never exceeded for any MOSFET
4. TC4427 GND must be tied to logic ground

To fulfill 1. TC4427 GND could be tied Q6 source (most negative battery voltage). With driver supply of 18V and battery charging voltage limited to e.g. 4.2 V per cell, the circuit can marginally work (fulfilling 2. and 3.). You can visualize individual Vgs values in a simulation. But it's a real bad design.

Hi. This answer is of great help to me.
Can you check if the things I understand are correct?

1. Sharing gnd of Tc4227 and gnd of Arduino.
2. Within the balancing circuit, the gnd is only connected to Q6. no the others.

Thank you for answering.

 

[KlausST]

Hi,

Why a new membership?
Why a new thread?

--> https://www.edaboard.com/threads/where-should-i-set-gnd.411238/post-1774891

Klaus

 

[jangmel]

Hi,

Why a new membership?
Why a new thread?

--> https://www.edaboard.com/threads/where-should-i-set-gnd.411238/post-1774891

Klaus

Hi.
I am team with him.
but I don't know his account, so I wanted to ask you additional questions about after the gate circuit was added.
I'm sorry if it's inconvenient.
Your response has been a great help to us. Thank you from the bottom of my heart.
We confirmed through the oscilloscope that the PWM past the gate driver has a suitable waveform, and we also added the dead time.
Also, I checked the data sheet for chips and MOSFETs. But I couldn't get information about the location of gnd. So I'm asking you again. Finally, thank you again, and I'd be very happy if you could be of service to us again.

 

[KlausST]

Hi,

to avoid negative voltages ...

--> GND should be the negative pin of BT3.

Only Q6 can be driven referenced to this GND. (called "LOW side driving")
All other Qs (Q1..Q5) need to be driven with floating supply (bootstrap). For all these you need to use a "HIGH side driver".

Be sure to create a path for charging the bootstrap capacitor (5x).

Klaus

 

[BradtheRad]

I tried many simulations to charge a battery pack (3 cells). Below is the best I've come up with. It's not a complete circuit but it demonstrates in basic terms what you're making. Rogue current flows are minimized. The clocks must be precisely timed. As bias signals they must reach certain volt levels (positive and negative), in order to turn the NPN's properly On-and-Off. Even so, cells seem to lose a few mA between gaining several mA.

As you can see no cell goes directly to a supply rail. Battery packs often have tack-welds between cells (which we hope to avoid breaking up when charging). I made long wires connecting the 3 cells directly together so that I could draw each stage separated and readily obvious. You would attach clips or pin-probes to a real battery pack when you equalize the cells.

I was unable to get mosfets to work in a similar simulation. Reason: The body diodes allow rogue current flows. The volt levels of three batteries add in series and send unwanted current at odd times to unexpected places.

I kept everything low voltage and low power. Perhaps you can find a way to raise the supply voltage and/or charge current, and also make other adjustments which keep charge rates manageable.

 

[D.A.(Tony)Stewart]

I see no purpose to this supposed BMS topology. The RLC circuit is very lossy and low Q so it is not useful to transfer a charge to a weaker cell. Only the strongest cells can be shorted to make them as weak as the weakest cell to balance them.