resize command - (VHDL)

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mstalebi

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vhdl resize

Dear friends,

can anyone help me understand how resize in VHDL works?

I want to know if this command generates reliable results for signed data types?

Thanks in advance,
msTalebi.
 

resize vhdl

I don't konw if resize works well for signed numbers but if you would like to perform sign extension i.e to place a smaller signed number into a larger one then it can be performed as follows:
Consider you want to place a 4-bit signed number into an 8-bit one:

process(smaller_num)
begin
larger_num(3 down to 0)<=smaller_num;
--places smaller number into the larger one.

--The next part performs the sign extension:
if (smaller_num(3)='0')
then
larger_num(7 downto 4)<="0000";
elsif(smaller_num(3)='1')
then
larger_num(7 downto 4)<="1111";
end if;

end process;
 
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