Resistor value for CPLD's latch up

[vaf20]

hello my friends
i use xilinx XC9500 series CPLD.this CPLD's work as interfaces between a general bus and other blocks.i used a resistor in each data line which get from bus as latch up resistor.i looked for a formula to figure out resistor value but nothing find.
any comment ?
BTW, what the other issue i should take in acount?
tnx in advance

 

[power-twq]

resistor for latchup

each FPGA chip has a latchup current specification,

you can calculate the resistor's value with the current requirement

for worst operating case.

best regards

hello my friends
i use xilinx XC9500 series CPLD.this CPLD's work as interfaces between a general bus and other blocks.i used a resistor in each data line which get from bus as latch up resistor.i looked for a formula to figure out resistor value but nothing find.
any comment ?
BTW, what the other issue i should take in acount?
tnx in advance

 

[vaf20]

cpld+latch

tnx amigo
could you show ma the link to XC9536 CPLD or spartanII FPGA latch up value?
TIA