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Resistor across crystal for biasing the internal op-amp

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Full Member level 6
May 10, 2020
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I've seen this below resistor across the terminal of the internal op-amp and also connected to the crystal.

I've read that this resistor is required to provide the biasing for the circuit so that the amplifier will work in the linear region.

From what I've read about biasing, with respect to BJT, biasing means setting up the voltages and current levels in the BJT circuit before the input signal is applied. But for biasing the op-amp, the voltages are already set by the supply pins right? What use would the resistor do just by connecting it to the input terminals?

enter image description here

Can someone explain me how it actually biases and makes the op-amp to work in linear region? Like what happens at the two ends of the resistor connected to the op-amp inputs?

It's an inverter gate, typically an unbuffered CMOS inverter, not an OP. The resistor is connected between input and output of the inverter and establishing negative DC feedback.
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I don't understand how you read an inverter symbol as OP and the resistor connected between OP inputs. You should know that an OP has three inputs. See below the internal circuit of a CMOS inverter:



I don't see the amolifier as Opamp, I rather see it as a digital inverter.
Maybe it's neither a oure Opamp and nor operated purely digital.

However ... it is an inverting amplifier. With relatively high gain.
Just for now forget about the capacitors and Xtal. Just imagine the input is a slow triangle waveform traveling from 0V to VCC.
At 0V input ... the output should be saturated at VCC (inverting)...and when the input is at VCC.. the output will be saturated at GND.
But in between ... there is a small range (let's say around 1.5V) where the amplifier really works in linear mode.

And this is the key point.
No back .. with capacitors and XTAL (but without resistors).
Now imagine that you take a piece of wire and short circuit C2 to GND. (You may test it, not dangerous to damage any part of the oscillator)
What happens: the amplifier input is LOW, the output is HIGH. Steady state.
Now remove the wire. The output still is HIGH but due to the high ohmic behaviour of the XTAL it can't charge C2 to get to 1.5V.
Bad situation. Oscillation stalled ... and you have to hope for some leakage current to slowly charge C2 to 1.5V for the output to go LOW.
As soon as the output goes LOW the oscillation will start.

To prevent from the stalled situation you need the resistor parallel to the XTAL. It ensures that the C2 always gets charged/ discharged to the 1.5V point.
This is called "biassing" here. ... and starts oscillation.

This stalled can happen by accident (wire). But it can also happen with slowly rising power supply. You may try this with an adjustable powersupply by slowly ramping up the supply voltage. (Or imagine a solar powered device where it may take several minutes for the supply voltage to rise to it's target.)

Many oscillator circuits rely on fast rising power supply acting as "kick start" for the oscillator. They may or may not start with slowly rising supply.
To avoid a stalled oscillator many oscillators have built in "biasing resistors".

For many applications it's not important how long it takes to start oscillation. They are happy even with a delay in the seconds.
But some applications need fast start of oscillation (maybe they stop oscillation to save power).
It's not unusual for an Xtal oscillator to take 200ms until the frequency is stable with low jitter.

While the one resistor just ensures that it will start, the second resistor (in series) can improve start up time until stable.

Many Xtal manufacturer provide more detailed design notes about this topic. They tell you how to calculate the values.
Just spend a minute to do a search.



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I've asked a similar question earlier in this forum. I went to read further articles and app notes regarding this and found the below image.


Here above, RFEXT is mentioned as "it is required to aid the startup of the oscillator & provides unfiltered feedback between the input and output of the amplifier. Oscillators require some kind of kick to start ringing"

Can someone tell me in simple term on how this RFEXT does this and the purpose of Rs and Rf ? Please explain in simple terms on how to understand this topic?


Rf and Rext accomplish biasing the CMOS gate into its active region, so that
it functions as an amplifier. Only one is needed. It also effects G of the overall

Rs is key to limiting power delivered to xtal/resonator so that it does not get damaged.
It also contributes to phase shift of the overall network.

Regards, Dana.

To build a crystal oscillator there's more than one approach. The single invert-gate method is just one.

By adding a second invert-gate we have another method which is not so finicky to get oscillations started. Parts count is less. I built this in hardware and it works with an inexpensive 32.768 kHz crystal.
(Usually this pulse generator is seen with a capacitor.)

The one-gate method can be made to operate at DC polarity which is seen as a benefit. However it then requires extra components so as to introduce just the right amount of instability so it oscillates. It's finicky by my experience.

crystal oscillator 2 invert-gates 40 kHz.png


Interesting circuit.
I understand that it will start without problems.
What I don't understand how it can work without the capacitors. The XTAL datasheets always give an operating capacitance.
I see that you mentioned the capacitors..

You say 32768 Hz XTAL .. but the simulation shows 40.5 kHz. Maybe the missing capacitors are the reason for this huge mismatch.
For me the reason to use an XTAL is the frequency accuracy. For XTALs this is in the region of 200 ppm (usually better), but here it is more than 230000 ppm. This is way more than a UART can bear.
If the deviation is true, then I'd rather use a simple RC oscillator. Cheaper, more accurate, better start up behaviour.


You say 32768 Hz XTAL .. but the simulation shows 40.5 kHz. Maybe the missing capacitors are the reason for this huge mismatch.

In hardware I obtain 32768 Hz from a crystal. Frequency is stable once adequate supply V is applied. Just a few Hz above and below on my frequency counter.
My invert-gate is 4069UBE (unbuffered, 6 on chip).

In simulation I started with the crystal model which I discovered in the recent version of Falstad's simulator. It's 10.1 MHz. I experiment with parameters in an effort to make it slower. However frequency varies with changing resistance nearby. No surprise that I need time to figure out its quirks.


10 MHz XTAL ... and 40 kHz output.
Then I guess it's rather the XTAL's series (stray) capacitance that determines the frequency, than it's resonance.


Too low a R value will de-Q the crystal and damp out oscillations
(but perhaps allow the inverter to amplify supply noise or close-in
signals). You'd definitely want to find the range on that, and stay
away from the cliff.

In my experience fed-back inverters have a pretty low gain (I see
A ~ 7-10 peak, in 0.6u-range CMOS). Your inverter's device geometry
would like to be optimized for gain peak (gm(pk)*Ro@pk) which
may likely be at longer L than a standard minimum inverter.

I have a hard time getting XOs to "kick" in simulation. An explicit
"kicker" (I like an ipulse, narrow and small, at t=10n) can help but
may hide the fact that a circuit's values prevent actually starting
if local noise is low. I've been told by guys who had experience at
integrated XO-port design, that they had a specific set of tricks
but they did not go so far as to share them (perhaps Mr. Googlez
is more forthcoming).

CD4000 logic may be a bit too slow (esp. at low Vdd) to make
the required single stage gain at 10MHz. If you are going to
work at low Vdd (5V and under) and higher fOsc, might try
substituting a single-stage 74HC or 74AC inverter if you can
ID one.

Be sure those two caps from xtal to GND plane are kept in place
w/ suitable values - that's where the oscillating current recirculates.
Poor quality caps, caps with too-low value for the crystal's needs,
these can damp an oscillation too.

The other missing point here is that if the resonant components are omitted, the input to the inverter can be driven by an external clock signal. The two inverter solution works using stray/parasitic capacitances with the mid(ish) point bias being provided by the first inverter but it can't be externally driven. I haven't tried it but I would guess the chances of biasing the input of single inverter solution with a potential divided would also work by why waste an extra component and lessen the chances of it 'self centering' by itself.


Another, finer point on XO simulation - I recall a hint that you
need to really crank down the tolerances, especially TRTOL, to
keep numerical noise from dominating and defeating the tank's
attempt (you hope) to "ring up". Sort of like the flip side of
"injection locking", you can have "injection unlocking" from
the TRAP method's sawtoothing.

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