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Resistance in vhdl programming for adc circuit

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Aritra17

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Suppose i'm designing a flash adc using vhdl programming in xilinx

then how am i supposed to make the resistances in vhdl

can i introduce ac signal in vhdl??how to do that??
 

alexan_e

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You mean to create an ADC peripheral inside the FPGA using VHDL... that is not possible,
you can only use VHDL to control an external ADC and read the digital result.

Alex
 

TrickyDicky

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VHDL is used for digital logic design. You can only synthesise digital logic into an FPGA.

VHDL can be used for very basic analogue modelling, like weak low and weak high (the 'L' and 'H' from std_logic) as inputs to your digital system and propogation delays, but none of this can be synthesised.
 

Aritra17

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i'm nt using any kit board

just for instance

the resistances in adc creates delay, so we can create a delay component and delay all the inputs using port map technique

actually i'm doing adc in tanner, i don't know the output pattern, i'm trying just randomly using vhdl what seems possible

but thanks for the advice
 

TrickyDicky

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you cannot create a reliable delay component, other pipeline delays using registers.
 

Aritra17

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ok,
but can any one of you please mail me a complete working circuit of a flash adc
can you please say how many comparators should i use in a 2bit flash adc,3 or 4??
what should i use in the generator block, how should i connect it with the comparators??

please help
 

alexan_e

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An FPGA can only interface with an ADC, provide the timing and display the result.
When i refer to the ADC I mean a complete ADC chip that includes all the necessary stages to make the measurement and convert it to a digital value,
this is why your comparator question doesn't make sense.
If you want to learn about the internal stricture of an ADC or you want to make your own ADC
with discrete components you should post in the analog section I think.

Alex
 

Aritra17

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im doing adc using tanner eda software
so it is chip designing technique
if you mean analog section as the hardware, using pre modified comparator chips
then sorry im not doing that
you must have heard about tanner eda software which is used for chip schematics&layout

for simplifying this tanner eda software i was trying the rtl using vhdl in schematics
 

alexan_e

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Actually i haven't but i have just checked it on the web,
it is an IC (simulation and) design software and I'm not involved in that in any way,
I only use simulation tools (proteus, orcad , NI etc)
and digital design like Xilinx ISE or ALtera Quartus etc..

This category has more to do with code for CPLD/FPGA
(Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.)

I think You should post to
ASIC Design Methodologies & Tools (Digital)
(ASIC (Application Specific Integrated Circuit) design methodologies
design tool (simulator, synthesis...) related questions)

or to
Analog IC Design & Layout
Analog IC design & Layout questions.
(Analog ASIC design. Semiconductor Technology issues.)

Alex
 
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