resetting values in a VHDL register and stop writing further

[sdram]

I have simple register and getting single bit values from 5 state machines (all at one time). These values are stored in a register as std_logic_vector and has to be given as an input to another module. Once the output of this register is being processed in another module, the index in the register where there was a change (e,g 0 to 1), the value at that index should reset (e,g 1 to 0) and it should take no further input for that particular index (but there is constant input coming from state machines). Any suggestion, how it should be done?

Register code is:

entity fault_reg is
port (
  clk           : in  std_logic;
  rst           : in  std_logic;
  reg_in        : in  std_logic_vector(NUM_PORTS - 1 downto 0);
  reg_out       : out std_logic_vector(NUM_PORTS - 1 downto 0)
);
end fault_reg;

architecture Behavioral of fault_reg is
begin

reg_impl : process(clk, rst)
begin
    if rst = '1' then
        reg_out <= (others => '0');
    elsif clk'event and clk='1' then
        reg_out <= reg_in;
    end if;
end process reg_impl;

end Behavioral;

 

[FvM]

I think, you didn't yet manage to describe your problem clearly.

As far as I understand it's about edge respectively signal change detection of a single bit.

To clarify the intended design operation to you and others, you should sketch possible input waveforms and draw the expected output signal.

 

[sdram]

In simple words, how can I reset the value at a particular index of a register to 0 if the value at that index is 1. Also, how can I stop writing value at that index (because continuous input values are coming from another module) so that 0 which we have written, should not be overwritten.

 

[FvM]

Sketch a waveform!

Also, how can I stop writing value at that index (because continuous input values are coming from another module)

Why should "other modules" affect the value when each bit is processed independently?

 

[rca]

Well, first question, why you describe in vhdl the behavior of a flop?

you could write "a more complete" model with a data gating, and define a different reset value?

entity fault_reg is
generic ( c_reset_value : std_logic_vector(NUM_PORTS - 1 downto 0));
port (
  clk           : in  std_logic;
  rst           : in  std_logic;
  en           :  in std_logic;
  reg_in        : in  std_logic_vector(NUM_PORTS - 1 downto 0);
  reg_out       : out std_logic_vector(NUM_PORTS - 1 downto 0)
);
end fault_reg;

architecture Behavioral of fault_reg is
begin

reg_impl : process(clk, rst)
begin
    if rst = '1' then
        reg_out <= c_reset_value;
    elsif clk'event and clk='1' then
       if en='1' then  reg_out <= reg_in;
    end if;
end process reg_impl;

end Behavioral;

But beside that, you could create a synchrone process with a array of registers, and manipulated when the data need to be save or not.