RESET on FPGA! Where is ?

[speedman]

fpga reset

Hi all,

I'm new in FPGA and I bought a stater kit with spartan3.

There are many example to understand fpga but all of this are with external reset connect to the button.

So, my question : If I implement my design (State machine, Micro .....) who reset my HW. Clock is internal or external, but the reset ?

I've read on use of sync reset that is the best choice, but who generate it ?

I don't know....:|

 

[rberek]

all about reset on fpga

The reset signal is normally an input to the FPGA. How that is generated is completely up to you as a designer.

r.b.

 

[kel8157]

fpga soft reset

Hi all,

I'm new in FPGA and I bought a stater kit with spartan3.

There are many example to understand fpga but all of this are with external reset connect to the button.

So, my question : If I implement my design (State machine, Micro .....) who reset my HW. Clock is internal or external, but the reset ?

I've read on use of sync reset that is the best choice, but who generate it ?

I don't know....:|

Download the datasheet/reference manual of the board, they normally build a reset button with built-in debounce on it, and you can just use for the reset signal on the example designs without any special sync-reset.

 

[speedman]

reset in fpga

I 've sarched on datasheet and only phrase on reset is :

"In some applications, the BTN_SOUTH push-button switch is also a soft reset that
selectively resets functions within the FPGA."

So I think that for this board I will generate the reset pressing the button.

But....., How do it in a big fpga design.

Are there IC to generate a reset pulse ?

 

[FvM]

reset state machine

You didn't clarify your problem. A sync reset is a matter of FPGA design, not a hardware feature. In some cases, an external reset IC may be useful (e.g. with dubious startup behaviour of supply voltages), but it's not generally required, cause the FPGA has an internal POR (power on reset), that sets all FFs to a defined (usual '0') state. Cause it ocurs before any clock is present at the FPGA, it doesn't need to be synchronized.

In some designs, an additional sync reset after complete clock startup (including PLL/DCM clocks) may be required. It can be achieved by having an additional startup timer in the design that performs a systemwide reset (excluding itself!) after countdown. Read the FPGA user manuals regarding POR and initial state of registers, think about it, and you'll find a solution.

 

[speedman]

using power-on reset startup fpga

OK, I explain myn dubt.

In a custom board and external pin is dedicated to reset power IC.

So I wrote my vhdl src with a sync reset. But in a starter kit there is no pin or IC to reset.

Reading application note on fpga ( Spartan 3e Starter kit) is written that no reset is needed because fpga reset all internal logic after configuration.

What may I do ?

Erasing my reset src or maintein it ?

Where is the right way if now Im working on fpga implementation but I would pass to a real application ?

What may I do with the reset pin ?

I hope that I clarify my dubt....

 

[FvM]

internal reset fpga

Yes I see. The second paragraph in my above post is dedicated to the option of generating an internal synchronous reset derived from POR. But it may be completely superfluous in your application.