What is the syntax for reset array of record?
for example:
Code:
type record_slr is record
a : integer range 0 to 520;
b : integer range 0 to 780;
c : std_logic_vector(8 downto 0);
d : std_logic_vector(31 downto 0);
e : std_logic_vector(31 downto 0);
end record record_slr ;
type array_slr is array (0 to 37) of record_slr ;
signal slr: array_anchors ;
process(clk,nrst)
begin
if nrst= '0' then
-- ??
You can either review aggregate syntax in your favorite VHDL book or initialize record elements individually, you can even use loops if you don't remember how to access an array at once.
The former looks someway like this
Code VHDL - [expand]
1
slr <=(others=>(a =>0, b =>0, c =>(others=>'0), d =>(others=>'0), e =>(others=>'0)));