Requesting help| TI CD4094BE SIPO shift register problem

[Jordy121]

Hi there, I am using the CD4094BE SIPO shift register for a project of mine (I am an EE student), and i have this issue that when
data is low and i am giving 1 CP Q1-Q8 all turn to logic low instead of just shifting one LOW to Q1.
when shifting HIGH all is working well, my only problem is when data is low and CP is given all OUTPUTS turn LOW at once.

Schematic included please help me

 

[pinout]

As it works with a "1" input, but not with a "0" input I can see your frustration!
My instant thought was contact bounce, but that is not affected by the data in state.

At the moment my best suggestion is put some decoupling capacitors close the IC on the supply rail, in case switching is generating supply glitches and hence this symptom. Try 100nF.

If that doesn't help try reducing the Cap on the clock line. It is just possible that if the clock rise and fall times are too slow that this could cause some odd effects.
If debounce of the switch is an issue look in to some SR latchs made with cross coupled gates on the switch.

 

[Jordy121]

Thank you for your quick reply, I have tried what you have suggested, still no luck, it behaves the same.
Can you share your experience with this shift register or a similar one?
I have tried changing the IC to see if it is damaged, but a brand new one behaves the same way.

Schematic included to what you have suggested:



any suggestion will be HIGHLY appreciated!

thanks, Jordy.