omidrey
Newbie level 5
Dear All
Good day to you , I have recently prepared one VHDL code for implementing a digital clock and because I don't have any CPLD IC and its programmer , I wonder if any one can test the below code for me and then feedback to me whether the code is correctly working or not
List of Material :
4 seven segments
2 pushbuttons
1 switch
1 cpld / fpga IC
1 oscillator (default is 50 Mhz, obviously if this input clock changes, some change in the code should be taken so that we can have a true and correct 1 hz output to the internal circuits for counting the clock digits. )
Due to uploading limitations, I have changed the type of the file to txt so simply copy and paste content of the txt file in your vhdl synthesizer tool and go on.
I will appreciate if anyone can optimize my code for efficient power consumption and output heating.
I am looking forward hearing from you soon .
Best Regards
Omid
Good day to you , I have recently prepared one VHDL code for implementing a digital clock and because I don't have any CPLD IC and its programmer , I wonder if any one can test the below code for me and then feedback to me whether the code is correctly working or not
List of Material :
4 seven segments
2 pushbuttons
1 switch
1 cpld / fpga IC
1 oscillator (default is 50 Mhz, obviously if this input clock changes, some change in the code should be taken so that we can have a true and correct 1 hz output to the internal circuits for counting the clock digits. )
Due to uploading limitations, I have changed the type of the file to txt so simply copy and paste content of the txt file in your vhdl synthesizer tool and go on.
I will appreciate if anyone can optimize my code for efficient power consumption and output heating.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clockticks is Port ( set : in STD_LOGIC; clr : in STD_LOGIC; clock :in std_logic; BTN0 : in std_logic; ---Adjust Minutes BTN1 : in std_logic; ---Adjust Hours Seg1 : out std_logic_vector (6 downto 0); Seg2 : out std_logic_vector (6 downto 0); Seg3 : out std_logic_vector (6 downto 0); Seg4 : out std_logic_vector (6 downto 0)); end clockticks; architecture Behavioral of clockticks is -- Sec, Min, Hr Signals signal sec : std_logic_vector(5 downto 0); signal Min1Temp1 : std_logic_vector(3 downto 0); signal Min10Temp1: std_logic_vector(2 downto 0); signal Hr1Temp1 : std_logic_vector(3 downto 0); signal Hr10Temp1 : std_logic_vector(1 downto 0); signal Min1Temp2 : std_logic_vector(3 downto 0); signal Min10Temp2: std_logic_vector(2 downto 0); signal Hr1Temp2 : std_logic_vector(3 downto 0); signal Hr10Temp2 : std_logic_vector(1 downto 0); -- Main Outputs which will be used to generate 7segment code signal Hr1 : std_logic_vector(3 downto 0); -- 1's place signal Hr10 : std_logic_vector(3 downto 0); -- 10's place signal Min1 : std_logic_vector(3 downto 0); -- 1's place signal Min10 : std_logic_vector(3 downto 0); -- 10's place -- Clock Division signals signal temporal: STD_LOGIC; signal counter : integer range 0 to 25000000 := 0; -- Producing 1hz out of 50 Mhz oscillator signal clk : STD_LOGIC; begin -- Producing 1hz clock process (clr, clock) begin if (clr = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clock) then if (counter = 25000000) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; clk <= temporal; --Digital clock in VHDL process(clr, BTN0, set, clk ) --period of clk is 1 second.BTN0 begin if clr = '1' then Min1Temp1 <= "0000"; Min10Temp1 <= "000"; elsif set ='1' and (rising_edge(clk)) then if BTN0 = '0' then if Min1Temp1 < 9 then Min1Temp1 <= Min1Temp1 + 1; else Min1Temp1 <= "0000"; if Min10Temp1 < 5 then Min10Temp1 <= Min10Temp1 + 1; else Min10Temp1 <= "000"; end if; end if; end if; end if; end process; process(clr, BTN1, set, clk ) --period of clk is 1 second.BTN1 begin if clr = '1' then Hr1Temp1 <= "0000"; Hr10Temp1 <= "00"; elsif set ='1' then if BTN1 = '0' and (rising_edge(clk)) then if Hr1Temp1 < 9 then if Hr1Temp1 = 3 and Hr10Temp1 = 2 then Hr1temp1 <= "0000"; Hr10Temp1 <= "00"; else Hr1Temp1 <= Hr1Temp1 + 1; end if; else Hr1Temp1 <= "0000"; if Hr10Temp1 < 2 then Hr10Temp1 <= Hr10Temp1 + 1; else Hr10Temp1 <= "00"; end if; end if; end if; end if; end process; process(clk , clr ) -- clock begin if clr = '1' then sec <= "000000"; Min1Temp2 <= "0000"; Min10Temp2 <= "000"; Hr1Temp2 <= "0000"; Hr10Temp2 <= "00"; elsif ( BTN0 = '0' or BTN1 = '0') then Min1Temp2 <= Min1Temp1; Min10Temp2 <= Min10Temp1; Hr1Temp2 <= Hr1Temp1; Hr10Temp2 <= Hr10Temp1; else if (clk' event and clk ='1') then if sec >= 59 then if Min1Temp2 < 9 then Min1Temp2 <= Min1Temp2 + 1; else Min1Temp2 <= "0000"; if Min10Temp2 < 5 then Min10Temp2 <= Min10Temp2 + 1; else Min10Temp2 <= "000"; if Hr1Temp2 < 9 then if Hr1Temp2 = 3 and Hr10Temp2 = 2 then Hr1temp2 <= "0000"; Hr10Temp2 <= "00"; else Hr1Temp2 <= Hr1Temp2 + 1; end if; else Hr1Temp2 <= "0000"; if Hr10Temp2 < 2 then Hr10Temp2 <= Hr10Temp2 + 1; else Hr10Temp2 <= "00"; end if; end if; end if; end if; sec <= "000000"; else sec <= sec + 1; end if; end if; end if; end process; Min1 <= Min1Temp1 when (BTN0 = '0') else Min1Temp2 when (BTN0 = '1'); Min10 <= ('0' & Min10Temp1) when (BTN0 = '0') else ('0' & Min10Temp2) when (BTN0 = '1'); Hr1 <= Hr1Temp1 when (BTN1 = '0') else Hr1Temp2 when (BTN1 = '1'); Hr10 <= ("00" & Hr10Temp1) when (BTN1 = '0') else ("00" & Hr10Temp2) when (BTN1 = '1'); -- Display on segment process (clk,Min1) BEGIN if (clk'event and clk='1') then case Min1 is when "0000"=> Seg1 <="0000001"; -- '0' when "0001"=> Seg1 <="1001111"; -- '1' when "0010"=> Seg1 <="0010010"; -- '2' when "0011"=> Seg1 <="0000110"; -- '3' when "0100"=> Seg1 <="1001100"; -- '4' when "0101"=> Seg1 <="0100100"; -- '5' when "0110"=> Seg1 <="0100000"; -- '6' when "0111"=> Seg1 <="0001111"; -- '7' when "1000"=> Seg1 <="0000000"; -- '8' when "1001"=> Seg1 <="0000100"; -- '9' --nothing is displayed when a number more than 9 is given as input. when others=> Seg1 <="1111111"; end case; end if; end process; -- Display on segment process (clk,Min10) BEGIN if (clk'event and clk='1') then case Min10 is when "0000"=> Seg2 <="0000001"; -- '0' when "0001"=> Seg2 <="1001111"; -- '1' when "0010"=> Seg2 <="0010010"; -- '2' when "0011"=> Seg2 <="0000110"; -- '3' when "0100"=> Seg2 <="1001100"; -- '4' when "0101"=> Seg2 <="0100100"; -- '5' --nothing is displayed when a number more than 5 is given as input. when others=> Seg2 <="1111111"; end case; end if; end process; -- Display on segment process (clk,Hr1) BEGIN if (clk'event and clk='1') then case Hr1 is when "0000"=> Seg3 <="0000001"; -- '0' when "0001"=> Seg3 <="1001111"; -- '1' when "0010"=> Seg3 <="0010010"; -- '2' when "0011"=> Seg3 <="0000110"; -- '3' when "0100"=> Seg3 <="1001100"; -- '4' when "0101"=> Seg3 <="0100100"; -- '5' when "0110"=> Seg3 <="0100000"; -- '6' when "0111"=> Seg3 <="0001111"; -- '7' when "1000"=> Seg3 <="0000000"; -- '8' when "1001"=> Seg3 <="0000100"; -- '9' --nothing is displayed when a number more than 9 is given as input. when others=> Seg3 <="1111111"; end case; end if; end process; -- Display on segment process (clk,Hr10) BEGIN if (clk'event and clk='1') then case Hr10 is when "0000"=> Seg4 <="0000001"; -- '0' when "0001"=> Seg4 <="1001111"; -- '1' when "0010"=> Seg4 <="0010010"; -- '2' --nothing is displayed when a number more than 2 is given as input. when others=> Seg4 <="1111111"; end case; end if; end process; end Behavioral;
I am looking forward hearing from you soon .
Best Regards
Omid
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