[req] constraint expression in vera

[AlexWan]

There are some code with OpenVera. I can't know about the meaning.

enum ModeType {STOP = 1, DOZE = 2, DBUG = 4, RESET = 8, SOFTRESET = 16};
rand reg[31:0]       mode = 0;

  constraint mode_constraint {
     mode in {STOP, DOZE, DBUG, RESET,SOFTRESET,
              STOP | DOZE, STOP | DBUG, STOP | RESET,STOP | SOFTRESET,
              DOZE | DBUG, DOZE | RESET,DOZE | SOFTRESET,
              DBUG | RESET, DBUG | SOFTRESET,
              RESET |SOFTRESET};
   }

How to understand the "STOP | DOZE", "STOP | DBUG", ...? Could any one explain those code?

Thanks.

 

[aji_vlsi]

There are some code with OpenVera. I can't know about the meaning.

enum ModeType {STOP = 1, DOZE = 2, DBUG = 4, RESET = 8, SOFTRESET = 16};
rand reg[31:0]       mode = 0;

  constraint mode_constraint {
     mode in {STOP, DOZE, DBUG, RESET,SOFTRESET,
              STOP | DOZE, STOP | DBUG, STOP | RESET,STOP | SOFTRESET,
              DOZE | DBUG, DOZE | RESET,DOZE | SOFTRESET,
              DBUG | RESET, DBUG | SOFTRESET,
              RESET |SOFTRESET};
   }

How to understand the "STOP | DOZE", "STOP | DBUG", ...? Could any one explain those code?

Thanks.

Hi,
it is simple enumerated values - since "mode" is a 32-bit vector, the above constraint essentially means:

rand reg[31:0]       mode = 0;

  constraint mode_constraint {
     mode in {1, 2, 4, ..};
   }

Does that help?
Ajeetha, CVC
www.noveldv.com

 

[AlexWan]

Hi,
it is simple enumerated values - since "mode" is a 32-bit vector, the above constraint essentially means:

rand reg[31:0]       mode = 0;
  constraint mode_constraint {
     mode in {1, 2, 4, ..};
   }

For single enum element, mode is in {1,2,4,8,16}. But I want to know what's meaning of following:
"STOP | DOZE",
"STOP | DBUG",
"STOP | RESET",
"STOP | SOFTRESET",
"DOZE | DBUG",
"DOZE | RESET",
"DOZE | SOFTRESET",
"DBUG | RESET",
"DBUG | SOFTRESET",
"RESET |SOFTRESET".

Please give me some explain or information!
Thanks.

 

[aji_vlsi]

For single enum element, mode is in {1,2,4,8,16}. But I want to know what's meaning of following:
"STOP | DOZE",

Please give me some explain or information!
Thanks.

AlexWan,
It is an "expression", having said that perhaps your original code should have read:

STOP || DOZE than STOP | DOZE. As per VERA LRM, || is logical OR, | is bitwise OR. In any case, the meaning is what you get after that expression evaluation. Assuming it is ||, STOP || DOZE means, keep mode in wither STOP or DOZE.

Does that help?
Ajeetha, CVC
www.noveldv.com

 

[vivek]

i agree upon the '||' operator part, but little bit intrigued here. As per original code:

constraint mode_constraint { 
     mode in {STOP, DOZE, DBUG, RESET,SOFTRESET, 
                   STOP | DOZE, STOP | DBUG, STOP | RESET,STOP | SOFTRESET, 
                   DOZE | DBUG, DOZE | RESET,DOZE | SOFTRESET, 
                   DBUG | RESET, DBUG | SOFTRESET, 
                   RESET |SOFTRESET};

What is the difference if i give it simply as :

constraint mode_constraint { 
     mode in {STOP, DOZE, DBUG, RESET,SOFTRESET};

What differnce will this make if i randomize?

 

[AlexWan]

For my opinion, "|" in this constraint is based on the logic. Maybe it is a parallel trigger.

Any one know this style??

 

[nand_gates]

The vera code is absulutely OK!
'|' is the correct choice here.

This is very common method used for register configuration!
I really wonder how so many peoples got confused!

Look at it this way!
The mode registers is a configuration register as
follows now I want to ceck various configurations.

+-----------+-------+------+------+------+
|   bit4    |  bit3 | bit2 | bit1 | bit0 |
+-----------+-------+------+------+------+
| SOFTRESET | RESET | DBUG | DOZE | STOP |
+-----------+-------+------+------+------+

1. STOP
2. DOZE
3. DBUG
4. RESET
5. SOFTRESET
6. STOP and DOZE
7. STOP and DBUG
8. STOP and RESET
9. STOP and SOFTRESET
10. DOZE and DBUG
11. DOZE and RESET
12. DOZE and SOFTRESET
13. DBUG and RESET
14. DBUG and SOFTRESET
15. RESET and SOFTRESET

Now check the code!

 

[AlexWan]

Hi nand_gates

How to explain the elements: RESET | SOFTRESET | DEBUG for your opinion????

 

[nand_gates]

Hi,
According to the definition of mode config register there are 32 possible
configuration values. Out of which the tester only wants to verify few combinations only!
"RESET | SOFTRESET | DEBUG" is also a valid configuration value.