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Relation betweek low Vt and leakage?

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singu31

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low vt high vt

Hi,

I went through a couple of papers on Multiple Vt CMOS structures for low power design. In all of these they say that scaling down supply voltage reduces power consumption as

Power α (VDD)^2.

But as we scale down supply voltage we also have to scale down Vt.

I dont understand exactly why the leakage current increases as we scale down Vt? Why do high Vt transistors have lesser leakage than Low Vt transistors?

Please clarify.

Thanks

Singaravelan
 

v_c

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I think what you are dealing with here is the increase in leakage due to sub-threshold operation. I recently posted an answer to a very similar question
on the board in the "Analog Circuit Design" section. Here's the link



I hope this helps you out.

Best regards,
v_c
 

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