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Register retiming in DC ( Optimize Register )

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Karthi

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register retiming + dc

Hi,
I face a problem while retiming using optimize_register command in DC. There is a stage in my pipelined design such that its slack is negative and the subsequent stages have a positive slack. When i execute the command "optimize_register", i get the following warning :
The following registers are considered to be 'fixed' during retiming. They are end-points of timing exceptions such as 'set_false_path'. (RTDC-34).

But i did not give any false, multicycle path in my design. I ve not used set_min, max_delay also. Can anyone please help me out to solve this issue??/
 

jackson_peng

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register retiming + dc + command

follow the userguide, use "report_timing_requirements" to check the constrain on registers.

i guess maybe the "set_dont_touch" would also get the same problem
 

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