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sebas

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Hi,

In my code I have a register that is written with data read from SPI (register is 32bit and loaded after all the 32 bits have been read from SPI in a temp register). On the other side the register is read by the wishbone interface. My question is: do I have to worry that the data can be metastable at the time of the read, because its just being written? Should I use something like read on posedege, write on negedge? If not why? The register, I guess, would be implemented as a set of flipflops so the new data would be loaded in parallel....

Thanks
 

hi
metastability could occur in multiple clock design (when signal cross different clock domains) or if You have asynchronous data input of a trigger. If You want to use "different edge sensitive" triggers You should worry about if Your data signal between them has delay > Period/2. hope I understand Your question correctly.
 
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Hi,

thanks for the response. maybe metastability was not the perfect word, I know the metastability occurs in multiple clock domain design. My question was if I have something to worry about in a design where I have the same clock (both wishbone and SPI work on the same clock).
 

If You want to use "different edge sensitive" triggers You should worry about if Your data signal between them has delay > Period/2.
 

I don't want to use different edge sensitive triggers I just suggested that as a solution if there would be problems. But, I know realize that my question was a bit stupid, the fact that both transfers (read and write) occur in the same clock domain it's enough to guarantee the data is valid, right?
 

I am dealing with Xilinx FPGAs, it is a good design practice to use timing constraints, in Your case Period constraint(max design frequency). If some path in design violates time requirements, during synthesis process errors will appear. If errors do not appear, Xilinx guarantee stable work.
 

I'm working on Xilinx too. So, if I have a design constraint that sets the max frequency to be the frequency of the whisbone clock and the design passes synthesis without errors then I'm guaranteed stable work?
 

I think so. Try it)
"Try it" is a imprescriptible part of development process)
 

With regard to using different edges in the same design... A good design practice generally would be to stick to one specific edge for most of the logic. Typically that would be posedge. Some exceptions could be reset circuits or some such. Also, timing analysis might require more attention when you start mixing things.

Is this because your own stuff uses one particular edge all over the place, and some other 3rd party stuff uses the other particular edge? If yes, personally I would put the 3rd party stuff in a wrapper module so it conformed to my own standard for this project...
 

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