register or latch compare with memory?

[floatgrass]

i want to know why people use memory in design rather than register or latch.
less area or speed ?
thanks

 

[armer]

memory

If the memory is small, like 4 work fifo, you can use register to implement it, but when the memory cell is large, we should use memory.
because it is optimized.
As we know, memory is optimized, so the address decode is efficient.
as we use many register to implement memory. the cell will have large area. and the address decode scheme is not efficient as use memory.

 

[S0933263236]

area compare (use the no. of MOS FET) :
1. sram memory cell (1 bit) for embeded sram logic process
=> 6 MOS FETs
2. for UMC 0.5um GlobeCAD standcell library :
RL_DFFRBP(D Flip-Flop with Asyn. /Reset) => 30 MOS FETs
RL_DLHRBN(D Latch Active High With /Reset) => 20 MOS FETs

PS: The size of MOS FET used in standard-cell library is larger than
memory-cell MOS FET also.

 

[floatgrass]

thanks
i understand your words.
so what usage is the memory .db and .v library? i know .v is used for timing simulation,but memory .db library is used for what?
please instruct me

 

[S0933263236]

1. .db file for Design Compiler => binary file format for cell libary or
design database. (Design compiler is a digital-only tool)
2. .v file => means Verilog file normally , it can be :
(1) verilog simulation model
(2) synthsizable design file
(3) verilog netlist
3. Memory block can be generated by memory compiler or memory designers, and it should have a simulation model(Verilog or VHDL) to be co-simulated with other block (Digital or Mix).

 

[floatgrass]

there is a memory in my design ,so i must isolate the memory module from other module during the synthesis? if it is yes and not systhesize the memory module ,,so dc produce the sdf file without the memory timing.how will i do with it ? i must simulate it use memory .v library ? but memory .db library no use.

 

[floatgrass]

there is a memory in my design ,so i must isolate the memory module from other module during the synthesis? if it is yes and not systhesize the memory module ,,so dc produce the sdf file without the memory timing.how will i do with it ? i must simulate it use memory .v library ? but memory .db library be not used. I puzzle.